Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 91
- Seite / 196
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
Signal Name Direction Description
tx_in_ptp_
overwrite[1:0]
Input If the current packet is a 1588 PTP packet, indicates to the TX
MAC what it should do to generate the packet exit timestamp in
one-step mode. The IP core is in one-step mode when the ptp_s2
field in bit [1] of the TX_PTP_STATUS register has the value of 0.
The correct action depends on the system-level application. The
client indicates the desired action with the following valid values:
• 2'b00: Add the internally maintained timestamp information to
the timestamp information in the incoming packet and write
the resulting timestamp in the outgoing packet. Exit timestamp
= entry timestamp plus expected latency through the IP core
plus user-defined value in TX_PTP_EXTRA_LATENCY register.
• 2'b01: Overwrite the timestamp in the outgoing packet with the
sum of the timestamp from the incoming packet plus the value
the IP core would calculate for the 2'b00 value. Exit timestamp
= (2 x entry timestamp) plus expected latency through the IP
core plus user-defined value in TX_PTP_EXTRA_LATENCY
register. This option is useful when the receiving application
performs the subtraction after receiving the packet.
• 2'b10: Reserved.
• 2'b11: Overwrite the timestamp in the outgoing packet with the
difference of the value the IP core would calculate for the 2'b00
value and the entry timestamp. Exit timestamp = (entry
timestamp plus expected latency through the IP core plus user-
defined value in TX_PTP_EXTRA_LATENCY register) minus the
entry timestamp, which equals the expected latency through
the IP core plus user-defined value in TX_PTP_EXTRA_LATENCY
register. This option is useful when the receiving application
calculates the cumulative latency.
For 1588 PTP packets, the TX client must maintain the desired
value on this signal while the TX SOP signal is asserted.
tx_in_ptp_
offset[15:0]
Input If the current packet is a 1588 PTP packet, indicates the offset of
the timestamp information in the packet. Depending on the value
on the tx_in_ptp_overwrite signal, the IP core overwrites the
96-bit value at this offset or combines it with the IP core internal
timestamp information. For 1588 PTP packets, the TX client must
maintain the desired value on this signal while the TX SOP signal
is asserted.
The TX client must ensure that the timestamp bytes and the TCP
checksum bytes in the packet do not overlap. The IP core does not
check for overlap. If these two fields overlap, the results are
undefined.
3-46
1588 PTP Interface Signals
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
Verwandte Produkte und Handbücher für Messgeräte Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore
Messgeräte Altera JNEye Bedienungsanleitung
(194 Seiten)
(194 Seiten)
Messgeräte Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Bedienungsanleitung
(413 Seiten)
(413 Seiten)
Messgeräte Altera Mentor Verification IP Altera Edition AMBA AXI4-St Bedienungsanleitung
(231 Seiten)
(231 Seiten)
Messgeräte Altera Nios II Bedienungsanleitung
(22 Seiten)
(22 Seiten)
Messgeräte Altera Nios II Bedienungsanleitung
(22 Seiten)
(22 Seiten)
Messgeräte Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Bedienungsanleitung
(783 Seiten)
(783 Seiten)
Messgeräte Altera PCI Development Kit, Cyclone II Edition Getting St Bedienungsanleitung
(40 Seiten)
(40 Seiten)
Messgeräte Altera PCI Express Development Kit, Stratix II GX Edition Bedienungsanleitung
(36 Seiten)
(36 Seiten)
Messgeräte Altera PCI Compiler Bedienungsanleitung
(360 Seiten)
(360 Seiten)
© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.033 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern