Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 74
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Figure 3-18: The XOFF and XON Pause Frames for Standard Flow Control
XOFF Frame XON Frame
START[7:0] START[7:0]
PREAMBLE[47:0] PREAMBLE[47:0]
SFD[7:0] SFD[7:0]
DESTINATION ADDRESS[47:0] =
0x010000C28001
(3)
DESTINATION ADDRESS[47:0] =
0x010000C28001
SOURCE ADDRESS[47:0] SOURCE ADDRESS[47:0]
TYPE[15:0] = 0x8808 TYPE[15:0] = 0x8808
OPCODE[15:0] = 0x001 (standard FC) OPCODE[15:0] = 0x001 (standard FC)
PAUSE QUANTA[15:0] = 0xP1, 0xP2
(4)
PAUSE QUANTA[15:0] = 0x0000
PAD[335:0] PAD[335:0]
CRC[31:0] CRC[31:0]
Figure 3-19: The XOFF and XON Pause Frames for Priority Flow Control
XOFF Frame
XON Frame
START[7:0] START[7:0]
PREAMBLE[47:0] PREAMBLE[47:0]
SFD[7:0] SFD[7:0]
DESTINATION ADDRESS[47:0] =
0x010000C28001
(3)
DESTINATION ADDRESS[47:0] =
0x010000C28001
SOURCE ADDRESS[47:0] SOURCE ADDRESS[47:0]
TYPE[15:0] = 0x8808 TYPE[15:0] = 0x8808
OPCODE[15:0] = 0x0101 (PFC) OPCODE[15:0] = 0x0101 (PFC)
PRIORITY_ENABLE[15:0]
(5)
PRIORITY_ENABLE[15:0]
(6)
TIME0[15:0]
(7)
TIME0[15:0] = 0x0000
... ...
TIME7[15:0]
(7)
TIME7[15:0] = 0x0000
PAD[207:0] PAD[207:0]
CRC[31:0] CRC[31:0]
(3)
This is a multicast destination address.
(4)
The bytes P1 and P2 are filled with the value configured in the TX_PAUSE_QUANTA register.
(5)
Bit [n] has the value of 1 if the TIMEn field is valid.
(6)
Bit [n] has the value of 1 if the XON request applies to priority queue n.
(7)
The TIMEn field is filled with the value available in the TX_PAUSE_QUANTAregister when the TX_PAUSE_
QNUMBER register holds the value of n.
UG-01172
2015.05.04
Congestion and Flow Control Using Pause Frames
3-29
Functional Description
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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