Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 110)

Table 3-19: Low Latency 40-100GbE IP Core Address Map

Lists the memory mapped registers for the Low Latency 40-100GbE IP core. Each register is 32 bits, and the

addresses (word offsets) each address a full word. This table does not list the Revision ID, scratch, and name

registers present in each of the address ranges at offsets 0x00, 0x01, and 0x02–0x04 respectively. However, those

registers appear in the detailed listings with descriptions.

Word Offset Register Description

0x0B0–

0x0BD

40GBASE-KR4 top-level and FEC registers

Accessible only if you turn on Enable KR. FEC registers are accessible only if you also turn

on Include FEC sublayer.

0x0BE–

0x0BF

Reserved.

0x0C0–

0x0CC

40GBASE-KR4 auto-negotiation registers

Accessible only if you turn on Enable KR and Enable Auto-Negotiation.

0x0CD–

0x0CF

Reserved.

0x0D0–

0x0EB

40GBASE-KR4 link training registers

Accessible only if you turn on Enable KR and Enable Link Training.

0x0EC–

0x0FF

Reserved.

0x310–

0x344

PHY registers available in all IP core variations

0x405 Link fault signaling register LINK_FAULT_CONFIG

Accessible only if you turn on Enable link fault generation

0x406 IPG column removal register IPG_COL_REM

Accessible only if you turn on Average interpacket gap

0x407 TX maximum size Ethernet frame (in bytes) MAX_TX_SIZE_CONFIG. Value determines

whether the IP core increments the CNTR_TX_OVERSIZE register

0x506 RX maximum size Ethernet frame (in bytes) MAX_RX_SIZE_CONFIG. Value determines

whether the IP core increments the CNTR_RX_OVERSIZE register.

0x507 RX CRC forwarding configuration register MAC_CRC_CONFIG

0x508 Link fault status register

Provides link fault status information if you turn on Enable link fault generation. Returns

zeroes if you turn off Enable link fault generation.

UG-01172

2015.05.04

Software Interface: Registers

3-65

Functional Description

Altera Corporation

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