Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 53)

Table 3-2: Signals of the TX Client Interface

In the table, <n> = 4 for the 40GbE IP core and <n> = 8 for the 100GbE IP core. <l> is log

(8*<n>). All interface

signals are clocked by the clk_txmac clock.

Signal Name Direction Description

l<n>_tx_data[<n>*64-1:0]

Input TX data. If the preamble pass-through feature is enabled,

data begins with the preamble.

The Low Latency 40-100GbE IP core does not process

incoming frames of less than nine bytes correctly. You

must ensure such frames do not reach the TX client

interface.

You must send each TX data packet without intermediate

idle cycles. Therefore, you must ensure your application

can provide the data for a single packet in consecutive

clock cycles. If data might not be available otherwise, you

must buffer the data in your design and wait to assert l<n>

_tx_startofpacket when you are assured the packet data

to send on l<n>_tx_data[<n>*64-1:0] is available or

will be available on time.

l<n>_tx_empty[<l>-1:0]

Input Indicates the number of empty bytes on l<n>_tx_data

when l<n>_tx_endofpacket is asserted.

l<n>_tx_startofpacket

Input When asserted, indicates the start of a packet. The packet

starts on the MSB.

l<n>_tx_endofpacket

Input When asserted, indicates the end of packet.

l<n>_tx_ready

Output When asserted, the MAC is ready to receive data. The

l<n>_tx_ready signal acts as an acknowledge. The source

drives l<n>_tx_valid and l<n>_tx_data[<n>*64-1:0],

then waits for the sink to assert l<n>_tx_ready. The

readyLatency is zero cycles, so that the IP core accepts

valid data in the same cycle in which it asserts l<n>_tx_

ready.

The l<n>_tx_ready signal indicates the MAC is ready to

receive data in normal operational model. However, the

l<n>_tx_ready signal might not be an adequate

indication following reset. To avoid sending packets

before the Ethernet link is able to transmit them reliably,

you should ensure that the application does not send

packets on the TX client interface until after the tx_

lanes_stable signal is asserted.

l<n>_tx_valid

Input When asserted l<n>_tx_data is valid. This signal must be

continuously asserted between the assertions of l<n>_tx_

startofpacket and l<n>_tx_endofpacket for the same

packet.

3-8

Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)

UG-01172

2015.05.04

Altera Corporation

Functional Description

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