Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 101
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Figure 3-28: Top-Level Signals of the Low Latency 40-100GbE IP Cores
In the figure, <n> = 4 for the 40GbE IP cores and <n> = 8 for the 100GbE IP cores. <l> is log
2
(8*<n>). In
the custom streaming client interface, <w> = 2 for the 40GbE IP core and <w> = 4 for the 100GbE IP
core. <v> is the number of transceiver PHY links (4 for 40GbE and CAUI-4 IP cores, and 10 for standard
100GbE IP cores). <N> is the number of priority flow control queues. (<N> = 1 for IP cores configured
with standard flow control or with no flow control, and <N> = the value of the relevant parameter for IP
cores configured with priority-based flow control).
Low Latency 40-100GbE IP Core
rx_serial [<v>-1:0]
tx_serial [<v>-1:0]
Asynchronous
Reset Signal
Avalon-MM
Control
and Status
Interface
Pause Control
and Generation
1588 Precise Timing
Protocol Interface
Link Fault Signaling
reset_async
status_addr [15:0]
reset_status
status_read
status_write
status_writedata [31:0]
status_readdata [31:0]
status_readdata_valid
status_waitrequest
status_read_timeout
Avalon-MM
Arria10
Transceiver
Reconfiguration
Interface
reconfig_address[13:0]
reconfig_reset
reconfig_from_xcvr
reconfig_to xcvr
reconfig_read
reconfig_write
reconfig_writedata [31:0]
reconfig_readdata [31:0]
reconfig_waitrequest
pause_receive_rx[<N>-1:0]
pause_insert_tx[<N>-1:0]
remote_fault_status
local_fault_status
Transceiver Serial
Data <v> lanes
@ 10.3125 Gbps or
25.78125 Gbps
Increment Vectors of
Statistics Counters
rx_statistic_counters[26:0]
tx_statistic_counters[21:0]
ptp_pkt_out
tx_in_ptp_offset[15:0]
tx_in_ptp_overwrite[1:0]
tx_in_ptp
tod_tx_clk_st2[95:0]
rx_tod[95:0]
RX PHY Status
rx_pcs_ready
TX Avalon-ST
Client Interface
RX Avalon-ST
Client Interface
l<n>_tx_data[(64 x <
n>)-1:0]
l<n>_tx_empty[<
l>-1:0]
l<n>_tx_startofpacket
l<n>_tx_endofpacket
l<n>_tx_ready
l<n>_tx_valid
l<n>_rx_data[(64 x <n>)-1:0]
l<n>_rx_empty[<l>-1:0]
l<n>_rx_startofpacket
l<n>_rx_endofpacket
l<n>_rx_error[5:0]
l<n>_rx_valid
l<n>_rx_fcs_valid
l<n>_rx_fcs_error
l<n>_rx_status[2:0]
l<n>_tx_error
TX Custom
Client Interface
RX Custom
Client Interface
din[(64 x <w>)-1:0]
din_sop[<w>-1:0]
din_eop[<w>-1:0]
din_eop_empty[11:0]
din_idle[<w>-1:0]
tx_error[<w>-1:0]
din_req
dout_d[(64 x <w>)-1:0]
dout_c[(8 x <w>)-1:0]
dout_sop[<w>-1:0]
dout_eop[<w>-1:0]
dout_eop_empty[<w>-1:0]
dout_idle[<w>-1:0]
rx_fcs_error
rx_fcs_valid
rx_status[2:0]
dout_valid
Clocks
clk_txmac_in
clk_rxmac
clk_rx_recover
clk_status
reconfig_clk
clk_ref
External PLL Interface
for Arria 10 Devices
Interface to Stratix V
Transceiver Reconfiguration
Controller
tx_serial_clk [<v>-1:0]
pll_locked
rx_inc_octetsOK[15:0]
tx_inc_octetsOK[15:0]
rx_inc_octetsOK_valid
tx_inc_octetsOK_valid
OctetOK Count Interface
unidirectional_en
link_fault_gen_en
tod_txmac_in
tod_rxmac_in
tx_in_zero_tcp
tx_in_tcp_offset[15:0]
clk_txmac
rx_error[5:0]
tx_lanes_stable
3-56
Low Latency 40-100GbE IP Core Signals
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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