Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 27)

Parameter Type Range Default

Setting

Parameter Description

Set FEC_Enable

bit on power up

or reset

Boolean • True

• False

True

If this parameter is turned on, the IP core sets the

FEC enable bit (40GBASE-KR4 register offset 0xB0,

bit 18: KR FEC request) on power up and reset. If

you turn on this parameter but do not turn on Set

FEC_ability bit on power up or reset, this parameter

has no effect: the IP core cannot specify the value of 1

for FEC Requested without specifying the value of 1

for FEC Ability.

This parameter is available if you turn on Include

FEC sublayer.

Table 2-3: 40-100GbE PHY Parameter Settings

Lists the PHY parameters that are configured automatically based on parameter values you select in the Low

Latency 40G/100G Ethernet parameter editor.

Parameter 40GbE Value

40GBASE-KR4 Value

100GbE Value 100GbE at CAUI–4

Lanes

4 10 4

Data rate per lane

10312.5 Mbps 10312.5 Mbps 25781.25 Mbps

Available PHY

reference clock

frequencies

322.265625 MHz

644.53125 MHz

322.265625 MHz

644.53125 MHz

322.265625 MHz

644.53125 MHz

Related Information

Clocks on page 3-51

The PHY reference frequency value is the required frequency of the transceiver reference clock or

transceiver reference clocks.

Files Generated for Stratix V Variations

The Quartus II software generates the following output for your Stratix V LL 40-100GbE IP core.

UG-01172

2015.05.04

Files Generated for Stratix V Variations

2-13

Getting Started

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