Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 25
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Parameter Type Range Default
Setting
Parameter Description
Pause ability–
C1
Boolean • True
• False
True If this parameter is turned on, the IP core indicates
on the Ethernet link that it supports asymmetric
pauses as defined in Annex 28B of Section 2 of IEEE
Std 802.3–2008.
Link Training: PMA Parameters
VMAXRULE Integer
0–31 30
Specifies the maximum V
OD
. The default value, 60,
represents 1200 mV.
VMINRULE Integer
0–31 6
Specifies the minimum V
OD
. The default value, 9,
represents 165 mV.
VODMINRULE Integer
0–31 14
Specifies the minimum V
OD
for the first tap. The
default value, 24, represents 440 mV.
VPOSTRULE Integer
0–25 25
Specifies the maximum value that the internal
algorithm for pre-emphasis will ever test in
determining the optimum post-tap setting.
VPRERULE Integer
0–16 16
Specifies the maximum value that the internal
algorithm for pre-emphasis will ever test in
determining the optimum pre-tap setting.
PREMAINVAL Integer
0–31 30
Specifies the Preset V
OD
value. This value is set by the
Preset command of the link training protocol,
defined in Clause 72.6.10.2.3.1 of IEEE Std 802.3ap–
2007.
PREPOSTVAL Integer
0–25 0
Specifies the preset Post-tap value.
PREPREVAL Integer
0–16 0
Specifies the preset Pre-tap value.
INITMAINVAL Integer
0–31 25
Specifies the initial V
OD
value. This value is set by the
Initialize command of the link training protocol,
defined in Clause 72.6.10.2.3.2 of IEEE Std 802.3ap–
2007.
INITPOSTVAL Integer
0–25 13
Specifies the initial Post-tap value.
INITPREVAL Integer
0–16 3
Specifies the initial Pre-tap value.
Link Training: General
UG-01172
2015.05.04
IP Core Parameters
2-11
Getting Started
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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