Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 7
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• Optional custom streaming data path interface with narrower bus width and a start frame possible on
64-bit word boundaries without the optional adapters. Interface has data width 128 or 256 bits
depending on the data rate.
• Support for jumbo packets.
• TX and RX CRC pass-through control.
• Optional TX CRC generation and insertion.
• RX CRC checking and error reporting.
• TX error insertion capability supports test and debug.
• RX and TX preamble pass-through options for applications that require proprietary user management
information transfer.
• TX automatic frame padding to meet the 64-byte minimum Ethernet frame length at the LL
40-100GbE Ethernet connection.
• Hardware and software reset control.
• Pause frame filtering control.
• Received control frame type indication.
• MAC provides cut-through frame processing.
• Optional deficit idle counter (DIC) options to maintain a finely controlled 8-byte or 12-byte inter-
packet gap (IPG) minimum average.
• Optional IEEE 802.3 Clause 31 Ethernet flow control operation using the pause registers or pause
interface.
• Optional priority-based flow control that complies with the IEEE Standard 802.1Qbb-2011—
Amendment 17: Priority-based Flow Control, using the pause registers for fine control.
• RX PCS lane skew tolerance that exceeds the IEEE 802.3-2012 Ethernet standard clause 82.2.12
requirements: 1900 bits RX lane skew tolerance for LL 40GbE IP cores and 1000 bits RX lane skew
tolerance for LL 100GbE IP cores.
• Optional support for the IEEE Standard 1588-2008 Precision Clock Synchronization Protocol (1588
PTP).
• Optional statistics counters.
• Optional fault signaling: detects and reports local fault and generates remote fault, with IEEE
802.3ba-2012 Ethernet Standard Clause 66 support.
• Optional serial PMA loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
The LL 40-100GbE IP core can support full wire line speed with a 64-byte frame length and back-to-back
or mixed length traffic with no dropped packets.
For a detailed specification of the Ethernet protocol refer to the IEEE 802.3ba-2010 High Speed Ethernet
Standard.
Related Information
IEEE website
The IEEE 802.3ba-2010 High Speed Ethernet Standard and the IEEE Standard 802.1Qbb-2011—
Amendment 17: Priority-based Flow Control are available on the IEEE website.
UG-01172
2015.05.04
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features
1-3
About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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