Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 12)

Table 1-5: IP Core FPGA Resource Utilization in Stratix V Devices

Lists the resources and expected performance for selected variations of the Low Latency 40-100GbE IP cores in a

Stratix V device.

These results were obtained using the Quartus II v14.1 software.

• The numbers of ALMs and logic registers are rounded up to the nearest 100.

• The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus II Fitter Report.

40GbE Variation ALMs Dedicated Logic

Registers

Memory

M20K

40GbE variation A 5300 12800 13

40GbE variation B 9900 21500 13

40GbE variation C 10900 24100 13

40GbE variation D 14000 31000 17

100GbE Variation ALMs Dedicated Logic

Registers

Memory

M20K

100GbE variation A

9500 23000 29

100GbE variation B

20900 48400 61

100GbE variation C 22100 52500 61

100GbE variation D

26900 63700 65

Related Information

Fitter Resources Reports in the Quartus II Help

Information about Quartus II resource utilization reporting, including ALMs needed.

Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores

Resource utilization changes depending on the parameter settings you specify in the Low Latency

40-100GbE parameter editor. For example, if you turn on pause functionality or statistics counters in the

LL 40-100GbE parameter editor, the IP core requires additional resources to implement the additional

functionality.

1-8

Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores

UG-01172

2015.05.04

Altera Corporation

About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function

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Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 12