Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 194
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Date Compatible ACDS
Version
Changes
2014.03.06 13.1 Update 3
13.1 Arria 10
Edition Update 2
• Corrected descriptions of pause enable registers:
• Added description for TX_XOF_EN register at offset 0x60A.
• Enhanced description of cfg_enable field of RX_PAUSE_ENABLE
register at offset 0x705 to clarify the different functions of the
TX_XOF_EN and RX_PAUSE_ENABLE registers in enabling the IP
core to incoming pause frames.
• Enhanced description of the TX_PAUSE_EN register at offset
0x605 to clarify the different functions of the TX_XOF_EN and TX_
PAUSE_EN registers.
• In "Differences Between Low Latency 40-100GbE IP Core and 40-
100GbE IP Core v13.1", enhanced the description of the differences
in pause frame control and processing and in use of maximum
frame size register information.
• Updated "Congestion and Flow Control Using Pause Frames" with
the enable register field information.
• Updated "Pause Control Frame Filtering" with the new enable
register field information and to clarify that by default, RX pause
frame processing is enabled.
• Enhanced "Low Latency 40-100GbE Example Project" to clarify that
some project aspects are relevant only for Arria 10 devices.
• Corrected "Clocks" section to include tx_serial_clk input clocks
and to list clk_rxmac and clk_txmac as output clocks.
2014.02.17
13.1 Update 3
13.1 Arria 10
Edition Update 2
Initial release.
How to Contact Altera
Table D-2: How to Contact Altera
To locate the most up-to-date information about Altera products, refer to this table. You can also contact your
local Altera sales office or sales representative.
Contact Contact Method Address
Technical support Website www.altera.com/support
Technical training
Website www.altera.com/training
Email [email protected]
Product literature Website www.altera.com/literature
D-8
How to Contact Altera
UG-01172
2015.05.04
Altera Corporation
Additional Information
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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