Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 109)

• Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface) on

page 3-24

• Pause Control and Generation Interface on page 3-30

Describes the pause signals available in the Low Latency 40-100GbE IP core.

• Link Fault Signaling Interface on page 3-32

• Statistics Counters Interface on page 3-34

• Control and Status Interface on page 3-49

• 1588 Precision Time Protocol Interfaces on page 3-38

• External Reconfiguration Controller on page 3-27

• Arria 10 Transceiver Reconfiguration Interface on page 3-51

• External Transceiver PLL on page 3-27

• Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

If you read this topic in the full user guide, links guide you to the descriptions of the individual signals,

by interface. Otherwise, refer to the user guide to find information about the signals.

Software Interface: Registers

This section provides information about the memory-mapped registers. You access these registers using

the IP core control and status interface. The registers use 32-bit addresses; they are not byte addressable.

Write operations to a read-only register field have no effect. Read operations that address a Reserved

registers that do not exist in your IP core variation have an unspecified result.

The following tables list the memory mapped registers for the Low Latency 40-100GbE IP core.

Table 3-18: Low Latency 40-100GbE IP Core Register Map Overview

Lists the main ranges of the memory mapped registers for the Low Latency 40-100GbE IP core. Register address

range 0x000–0x2FF is Reserved.

Word Offset Register Category

0x0B0–0x0FF 40GBASE-KR4 registers

0x300–0x3FF PHY registers

0x400–0x4FF TX MAC registers

0x500–0x5FF RX MAC registers

0x600–0x6FF TX flow control (pause functionality) registers ((If modify to byte addresses, this will

become 0x1800–0x1BFC; in fact, the final defined register in this range will now be

0x700–0x7FF RX flow control (pause functionality) registers

0x800–0x8FF TX statistics counters

0x900–0x9FF RX statistics counters

0xA00–0xAFF TX 1588 PTP registers

0xB00–0xBFF RX 1588 PTP registers

3-64

Software Interface: Registers

UG-01172

2015.05.04

Altera Corporation

Functional Description

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Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 109