Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung

Low Latency 40- and 100-Gbps EthernetMAC and PHY MegaCore Function UserGuideLast updated for Altera Complete Design Suite: 15.0SubscribeSend FeedbackU

Simulation EnvironmentAltera performs the following tests on the Low Latency 40-100GbE MAC and PHY IP core in thesimulation environment using internal

SignalsThis section lists the external signals of the different 40-100GbE IP core variations.Low Latency 40-100GbE IP Core Signals on page 3-55Low Lat

Figure 3-28: Top-Level Signals of the Low Latency 40-100GbE IP CoresIn the figure, <n> = 4 for the 40GbE IP cores and <n> = 8 for the 100G

Table 3-17: Low Latency 40-100GbE MAC and PHY IP Core SignalsSignal Name Direction Interfaceclk_refInput Clocksclk_rx_recover Output ClocksThis signal

Signal Name Direction Interfacedin_eop[<w>-1:0]Each IP core instance hasAvalon-ST TX and RX clientinterfaces, or custom streamingTX and RX clien

Signal Name Direction Interfacerx_status[2:0] Outputdout_validOutputpause_insert_tx[<N>-1:0]Input Pause control and generationinterfaceThese sig

Signal Name Direction Interfacetx_inc_mcast_data_errOutputtx_inc_mcast_data_okOutputtx_inc_bcast_data_errOutputtx_inc_bcast_data_okOutputtx_inc_ucast_

Signal Name Direction Interfacerx_inc_mcast_data_okOutputrx_inc_bcast_data_errOutputrx_inc_bcast_data_okOutputrx_inc_ucast_data_errOutputrx_inc_ucast_

Signal Name Direction Interfacestatus_addr[15:0]InputControl and status interfacestatus_readInputstatus_writeInputstatus_writedata[31:0]Inputstatus_re

reconfig_clkInput ClocksArria 10 Native PHY IP corereconfiguration interfaceThis signal is available in Arria10 devices only.reconfig_resetInput Reset

• Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface) onpage 3-24• Pause Control and Generation Interface on page

IP CoreVariationA B C D E FParameterEnable1588 PTP— — — On — —Enablelink faultgeneration— — On On — —EnableTX CRCinsertion— On On On On OnEnablepreamb

Table 3-19: Low Latency 40-100GbE IP Core Address MapLists the memory mapped registers for the Low Latency 40-100GbE IP core. Each register is 32 bits

Word Offset Register Description0x50A Enable RX payload length checking registerProvides enable bit to determine whether the RX error signal flags pay

• Pause Registers on page 3-85• TX Statistics Registers on page 3-92• RX Statistics Registers on page 3-98• 1588 PTP Registers on page 3-103• Arria 10

Addr Name Bit Description HW ResetValueAccess0x310 PHY_CONFIG[5] set_data_lock: Directs the PLL to lock to data.5'b0 RW[4] set_ref_lock: Directs

Addr Name Bit Description HW ResetValueAccess0x315 PHY_PCS_INDIRECT_DATA[3:0]or[9:0]PCS indirect data. To read a FIFO flag, set thevalue in the PHY_PC

Addr Name Bit Description HW ResetValueAccess0x340 PHY_REFCLK_KHZ[31:0] Reference clock frequency in KHz, assumingthe clk_status clock has the frequen

Table 3-22: Link Fault Status Register—Offset 0x508Name Bit Description HWResetValueAccessRemote FaultStatus[1] The remote fault status register. 1&ap

Table 3-23: LL 40-100GbE IP Core 40GBASE-KR4 Registers and Register Fields Not in Arria 10 10GBASE-KRPHY IP CoreDocuments the differences between the

Address Name Bit Description HWResetValueAccess0x0B1SEQ ReconfigMode[5:0][13:8] Specifies the Sequencer mode for PCSreconfiguration. The following mod

Address Name Bit Description HWResetValueAccessRCLR_ERRBLK_CNT, Lane 012 Writing a 1 resets the error blockcounters.Writing a 0 causes counting to res

Table 1-5: IP Core FPGA Resource Utilization in Stratix V Devices Lists the resources and expected performance for selected variations of the Low Late

Address Name Bit Description HWResetValueAccess• 6'b000000: 1000BASE-KX• 6'b000001: 10GBASE-KX4• 6'b000100: 10GBASE-KR• 6'b001000:

Address Name Bit Description HWResetValueAccessOvride LPCoef Enable[16] When set to 1, overrides the link partner'sequalization coefficients; sof

Address Name Bit Description HWResetValueAccessRestart Linktraining,Lane 3[3]This bit is the equivalent of register 0xD0[1] forLane 3.1'b0RW SC0x

Address Name Bit Description HWResetValueAccessUpdated RXCoef new,Lane 2[10]When set to 1, indicates that new local devicecoefficients are available f

Address Name Bit Description HWResetValueAccess0x0D4LDcoefficientupdate[5:0],Lane 0[5:0] Reflects the contents of the first 16-bit word ofthe training

Address Name Bit Description HWResetValueAccessLPCoefficientUpdate[5:0],Lane 0[21:16]Reflects the contents of the first 16-bit word ofthe training fra

Address Name Bit Description HWResetValueAccessLT VODMinovrd, Lane 0[12:8] Override value for the VODMINRULEparameter on Lane 0. When enabled, this va

Address Name Bit Description HWResetValueAccessLT VPre ovrdEnable, Lane0[29] When set to 1, enables the override value for theVPRERULE parameter store

Low Latency 40-100GbE IP Core MAC Configuration RegistersThe MAC configuration registers control the following MAC features in the RX and TX datapaths

Address Name Bit Description HW ResetValueAccess0x407MAX_TX_SIZE_CONFIG[15:0] Maximum size of Ethernet frames for CNTR_TX_OVERSIZE.If the IP core tran

Table 1-6: IP Core FPGA Resource Utilization in Arria 10 Devices Lists the resources and expected performance for selected variations of the Low Laten

Address Name Bit Description HWResetValueAccess0x507MAC_CRC_CONFIG[0] The RX CRC forwarding configuration register.Possible values are:• 1’b0: remove

Addr Name Bit Description HW ResetValueAccess0x602 TXSFC_NAME_0[31:0] First 4 characters of IP core variationidentifier string "40GSFCTxCSR"

Addr Name Bit Description HW ResetValueAccess0x606 TX_PAUSE_REQUEST[N-1:0](9)Pause request. If bit [n] of the TX_PAUSE_ENregister has the value of 1,

Addr Name Bit Description HW ResetValueAccess0x608 RETRANSMIT_XOFF_HOLDOFF_QUANTA[15:0] Specifies hold-off time from XOFF pauseframe transmission unti

Addr Name Bit Description HW ResetValueAccess0x60A ifyou set thevalue ofFlowcontrolmode toStandardflowcontrol inthe LL 40-100GbEparametereditor.TX_XOF

Addr Name Bit Description HW ResetValueAccess0x60B CFG_RETRANSMIT_HOLDOFF_EN[0]The CFG_RETRANSMIT_HOLDOFF_EN and CFG_RETRANSMIT_HOLDOFF_QUANTA registe

Addr Name Bit Description HW ResetValueAccess0x60F TX_PFC_SADDRL[31:0]TX_PFC_SADDRH contains the 16 most signifi‐cant bits of the source address for P

Addr Name Bit Description HW ResetValueAccessthe TX MAC to pause outgoing traffic on theTX Ethernet link. If you implement priority-based flow control

link is functioning properly. The statistics registers check the size of frames, which includes the followingfields:• Size of the destination address•

Address Name- Description Access0x809 CNTR_TX_MCAST_DATA_ERR_HINumber of errored multicast frames transmitted, excludingcontrol frames (upper 32 bits)

Release InformationTable 1-7: Low Latency 40‑100GbE IP Core Current Release InformationItem DescriptionVersion 15.0Release Date 2015.05.04OrderingCode

Address Name- Description Access0x818 CNTR_TX_65to127B_LONumber of transmitted frames between 65–127 bytes (lower32 bits)RO0x819 CNTR_TX_65to127B_HINu

Address Name- Description Access0x827 CNTR_TX_MCAST_DATA_OK_HINumber of valid multicast frames transmitted, excludingcontrol frames (upper 32 bits)RO0

Address Name- Description Access0x836 CNTR_TX_ST_LO Number of transmitted frame starts (lower 32 bits) RO0x837 CNTR_TX_ST_HI Number of transmitted fra

Related InformationStatistics Counters Interface on page 3-34RX Statistics RegistersThe RX statistics registers count RX Ethernet traffic and errors.

Address Name- Description Access0x906 CNTR_RX_CRCERR_LONumber of received frames with a frame of length at least64, with CRC error (lower 32 bits)RO0x

Address Name- Description Access0x916 CNTR_RX_64B_LO Number of 64-byte received frames (lower 32 bits),including the CRC field but excluding the pream

Address Name- Description Access0x924 CNTR_RX_OVERSIZE_LONumber of oversized frames (frames with more bytes thanthe number specified in the MAX_RX_SIZ

Address Name- Description Access0x934 CNTR_RX_RUNT_LO Number of received runt packets (lower 32 bits)A run is a packet of size less than 64 bytes but

Address Name- Description Access0x946CNTR_RX_STATUS • Bit [1]: Indicates that the RX statistics registers arepaused (while CNTR_RX_CONFIG[2] is assert

Addr Name Bit Description HW ResetValueAccess0xA05 TX_PTP_CLK_PERIOD[19:0] clk_txmac clock period.Bits [19:16]: nanosecondsBits [15:0]: fraction of na

Getting Started22015.05.04UG-01172SubscribeSend FeedbackThe following sections explain how to install, parameterize, simulate, and initialize the Low

Addr Name Bit Description HW ResetValueAccess0xB05 RX_PTP_CLK_PERIOD[19:0] clk_rxmac clock period.Bits [19:16]: nanosecondsBits [15:0]: fraction of na

Term DefinitionFrame Ethernet formatted packet. A frame consists of a start delimiter byte, a 7 bytepreamble, variable length data, 4-byte FCS, and an

Debugging the 40GbE and 100GbE Link42015.05.04UG-01172SubscribeSend FeedbackIf you are experiencing difficulties bringing up your Low Latency 40-100Gb

• Arria 10 Transceiver PHY User GuideFor information about the analog parameters for Arria 10 devices.4-2Debugging the 40GbE and 100GbE LinkUG-0117220

Low Latency 40-100GbE IP Core ExampleProjectA2015.05.04UG-01172SubscribeSend FeedbackAltera provides an example Quartus II project with the Low Latenc

Connections in the Low Latency 40-100GbE IP Core Example ProjectYou can use the example project to illustrate one correct method to connect your IP co

Figure A-2: High Level Block Diagram for the Arria 10 40-100GbE CAUI-4 Legacy Example ProjectThe non-device configurable example project for CAUI-4 va

Figure A-3: High Level Block Diagram for the Stratix V 40-100GbE Example ProjectThe example project for Stratix V variations includes a reconfiguratio

A single procedure generates both the testbench and the example project. The procedure varies dependingon your target device. To generate the testbenc

To set up, compile, and configure the project, follow these steps:1. Close the project in which you generated the example project. You cannot run the

Related InformationManaging Quartus II ProjectsRefer to the "Integrating IP Cores" section of this Quartus II Handbook chapter for more info

Arria 10 10GBASE-KR RegistersB2015.05.04UG-01172SubscribeSend FeedbackThis appendix duplicates the 10GBASE-KR PHY register listings from the Arria 10

The following table specifies the control and status registers that you can access over the Avalon-MMPHY management interface. A single address space

Table B-1: 10GBASE-KR Register DefinitionsWord Addr Bit R/W Name Description0x4B00RW Reset SEQ When set to 1, resets the 10GBASE-KR sequencer(auto rat

Word Addr Bit R/W Name Description0x4B10R SEQ Link Ready When asserted, the sequencer is indicating that thelink is ready.1 R SEQ AN timeout When asse

Word Addr Bit R/W Name Description0x4C00RW AN enable When set to 1, enables Auto Negotiation function.The default value is 1. For additional informati

Word Addr Bit R/W Name Description0x4C21RO AN page received When set to 1, a page has been received. When 0, apage has not been received. The current

Word Addr Bit R/W Name Description0x4C28 RO FEC negotiated –enable FEC from SEQWhen set to 1, PHY is negotiated to perform FEC.When set to 0, PHY is n

Word Addr Bit R/W Name Description0x4C315:0RW User base page low The Auto Negotiation TX state machine uses thesebits if the Auto Negotiation base pag

Word Addr Bit R/W Name Description0x4C5 15:0 RW User Next page low The Auto Negotiation TX state machine uses thesebits if the AN Next Page control bi

Word Addr Bit R/W Name Description0x4C9 15:0 RO LP Next page low The AN RX state machine receives these bits fromthe link partner. The following bits

Installing and Licensing IP CoresThe Altera IP Library provides many useful IP core functions for your production use without purchasingan additional

Word Addr Bit R/W Name Description0x4D00RW Link TrainingenableWhen 1, enables the 10GBASE-KR start-upprotocol. When 0, disables the 10GBASE-KR start-u

Word Addr Bit R/W Name Description0x4D014:12RW equal_cnt [2:0]Adds hysteresis to the error count to avoid localminimums. The following values are defi

Word Addr Bit R/W Name Description0x4D019:18RW Ctle depth When using CTLE fine-grained tuning, determineswhere to set final value in case of a tie. Th

Word Addr Bit R/W Name Description0x4D20RO Link Trained -Receiver statusWhen set to 1, the receiver is trained and is readyto receive data. When set t

Word Addr Bit R/W Name Description0x4D39:0RW ber_time_frames Specifies the number of training frames to examinefor bit errors on the link for each ste

Word Addr Bit R/W Name Description0x4D45:0ROorRWLD coefficientupdate[5:0]Reflects the contents of the first 16-bit word of thetraining frame sent from

Word Addr Bit R/W Name Description0x4D413:8RO LD coefficientstatus[5:0]Status report register for the contents of thesecond, 16-bit word of the traini

Word Addr Bit R/W Name Description0x4D421:16ROorRWLP coefficientupdate[5:0]Reflects the contents of the first 16-bit word of thetraining frame most re

Word Addr Bit R/W Name Description0x4D429:24RO LP coefficientstatus[5:0]Status report register reflects the contents of thesecond, 16-bit word of the

Word Addr Bit R/W Name Description0x4D527:24 R RXEQ CTLE Setting Most recent ctle_rc setting sent to the reconfigbundle during RX equalization.29:28 R

1. In the IP Catalog (Tools > IP Catalog), select a target device family.2. In the IP Catalog, locate and double-click the name of the IP core to c

Word Addr Bit R/W Name Description0x4D64:0RW LT VODMAX ovrd Override value for the VMAXRULE parameter.When enabled, this value substitutes for theVMAX

Word Addr Bit R/W Name Description0x4D6 to0x4FFReserved for 40G KR Left empty for address compatibility with 40GMAC+PHY KR solution.B-2210GBASE-KR PHY

Differences Between Low Latency 40-100GbEIP Core and 40-100GbE IP Core v15.0C2015.05.04UG-01172SubscribeSend FeedbackThe Low Latency 40-100GbE MegaCor

Property Low Latency 40-100GbE IP Core 40-100GbE IP Core v14.0Duplex mode Full duplex mode RX-only, TX-only, or full duplexmodeMAC client interface Av

Property Low Latency 40-100GbE IP Core 40-100GbE IP Core v14.0Maximum Ethernet frame sizeProgrammable maximum receivedframe size controls effect on th

Property Low Latency 40-100GbE IP Core 40-100GbE IP Core v14.0TX source address insertion Not available. The IP core transmitsthe source address provi

Property Low Latency 40-100GbE IP Core 40-100GbE IP Core v14.0Reset Single asynchronous reset signalresets the entire IP core. Additionalreset signals

Additional InformationD2015.05.04UG-01172SubscribeSend FeedbackLow Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCoreFunction User Guide Revision

Date Compatible ACDSVersionChanges• Added new TX error insertion feature. User logic can direct the IPcore to insert an error in an outgoing Ethernet

Date Compatible ACDSVersionChanges• Removed text of optimization parameter display initial blockfrom Optimizing the Low Latency 40-100GbE IP Core Simu

IP Core ParametersThe Low Latency 40-100GbE parameter editor provides the parameters you can set to configure the LowLatency 40-100GbE IP core and sim

Date Compatible ACDSVersionChanges• Added information about how the IP core handles malformedpackets it receives. Previously the IP core did not termi

Date Compatible ACDSVersionChanges• Clarified that IP core does not generate frames of eight bytes or less.• Added waveform to illustrate register acc

Date Compatible ACDSVersionChanges• Added new parameter option to configure priority-based flowcontrol. This option is available in 100GbE variations

Date Compatible ACDSVersionChanges• Corrected addresses of the following statistics registers:• CNTR_TX_CRCERR registers from 0x804-0x805 to 0x806-0x8

Date Compatible ACDSVersionChanges2014.03.06 13.1 Update 313.1 Arria 10Edition Update 2• Corrected descriptions of pause enable registers:• Added desc

Contact Contact Method AddressNontechnical support: softwarelicensingEmail [email protected] Information• www.altera.com/support• www.al

Visual Cue MeaningCourier typeIndicates signal, port, register, bit, block, andprimitive names. For example, data1, tdi, andinput. The suffix n denote

ContentsAbout the Low Latency 40- and 100-Gbps Ethernet MAC and PHYMegaCore Function...

Parameter Type Range Default Setting Parameter DescriptionEnable SyncEBoolean • True• FalseFalse Exposes the RX recovered clock asan output signal. Th

Parameter Type Range Default Setting Parameter DescriptionAverageinterpacketgapString • Disable deficitidle counter• 8• 1212 If you set the value of t

Parameter Type Range Default Setting Parameter DescriptionEnable TXCRC insertionBoolean • True• FalseTrue If turned on, the IP core inserts a32-bit Fr

Parameter Type Range Default Setting Parameter DescriptionEnable TXstatisticsBoolean • True• FalseTrue If turned on, the IP core includesbuilt–in TX s

Parameter Type Range DefaultSettingParameter DescriptionStatus clockrateFrequency range100–162MHz100MHzSets the expected incoming clk_status frequency

Parameter Type Range DefaultSettingParameter DescriptionPause ability–C1Boolean • True• FalseTrue If this parameter is turned on, the IP core indicate

Parameter Type Range DefaultSettingParameter DescriptionEnable LinkTrainingBoolean • True• FalseTrue If this parameter is turned on, the IP core inclu

Parameter Type Range DefaultSettingParameter DescriptionSet FEC_Enablebit on power upor resetBoolean • True• FalseTrueIf this parameter is turned on,

Figure 2-3: IP Core Generated FilesNotes:1. If generated for your IP variation<Project Directory><your_ip>_sim - IP core simulation files&

Figure 2-4: IP Core Generated Files<your_ip>.cmp - VHDL component declaration file<your_ip>.ppf - XML I/O pin information file<your_ip&

Compiling the Full Design and Programming the FPGA...2-31Initializing the IP Core...

File Name Description<system>.sopcinfo Describes the connections and IP component parameterizations inyour Qsys system. You can parse its conten

File Name Description<my_ip>.regmap If IP contains register information, .regmap file generates.The .regmap file describes the register map info

Clock Requirements for 40GBASE-KR4 Variations on page 2-21External TX MAC PLL on page 2-21Placement Settings for the Low Latency 40-100GbE IP Core on

You must also connect the mgmt_clk_clk and mgmt_rst_reset ports of the Altera Transceiver Reconfi‐guration Controller. The mgmt_clk_clk port must have

Note: If your Arria 10 design includes multiple instances of the LL 40-100GbE IP core, do not use theATX PLL HDL code provided with the IP core. Inste

TOD Module Signal LL 40-100GbE IP Core Signaltod_rxmclk[95:0] (output) tod_rxmac_in[95:0] (input)clk_txmac (input) clk_txmac (output)clk_rxmac (input)

hardware. You can run the testbench to observe the IP core behavior on the various interfaces insimulation.Altera offers testbenches for the following

Figure 2-5: Low Latency 40-100GbE non-40GBASE-KR4 IP Core TestbenchIllustrates the top-level modules of the Low Latency 40GbE and 100GbE example testb

Table 2-8: Low Latency 40-100GbE IP Core Testbench File DescriptionsLists the key files that implement the example testbenches.File Names DescriptionT

Figure 2-7: Typical 40GbE Traffic on the Avalon-ST InterfaceShows typical traffic from the simulation testbench created using the run_vsim.do script i

Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IPCore v15.0...

7. At marker 7, the 40GbE IP core asserts l4_rx_valid, indicating that it has valid data to send to theclient on l4_rx_data[255:0].8. At marker 8, the

Simulating the Low Latency 40‑100GbE IP Core With the TestbenchesYou can simulate the Low Latency 40-100GbE IP core using the Altera-supported version

Related InformationLow Latency 40-100GbE IP Core Testbenches on page 2-21Altera provides a testbench and an example project with most variations of th

• Low Latency 40-100GbE IP Core Example Project on page 5-1Altera provides an example Quartus II project with the Low Latency 40-100GbE IP core. This

The ModelSim-AE simulator does not have the capacity to simulate this IP core.Related InformationOptimizing the Low Latency 40-100GbE IP Core Simulati

# ** Sending Packet 6...# ** Sending Packet 7...# ** Sending Packet 8...# ** Sending Packet 9...# ** Sending P

Functional Description32015.05.04UG-01172SubscribeSend FeedbackThis chapter provides a detailed description of the Low Latency 40-100GbE IP core. The

High Level System OverviewFigure 3-1: Low Latency 40GbE and 100GbE MAC and PHY IP CoresMain blocks, internal connections, and external block requireme

The Low Latency 40-100GbE IP core includes the following interfaces:• Datapath client-interface–The following options are available:• 40GbE with adapt

Figure 3-2: Typical Client Frame at the Transmit InterfaceIllustrates the changes that the TX MAC makes to the client frame. This figure uses the foll

About the Low Latency 40- and 100-GbpsEthernet MAC and PHY MegaCore Function12015.05.04UG-01172SubscribeSend FeedbackThe Altera® Low Latency 40- and 1

provides the length of the payload data that ranges from 0–1500 bytes. The TX MAC does not modify thisfield before forwarding it to the network.Frame

error appears as a 66-bit error block that consists of eight /E/ characters (EBLOCK_T) in the Ethernetframe.To direct the IP core to insert a TX error

Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)The Low Latency 40-100GbE IP core TX datapath with adapters employs the A

Table 3-2: Signals of the TX Client InterfaceIn the table, <n> = 4 for the 40GbE IP core and <n> = 8 for the 100GbE IP core. <l> is

Signal Name Direction Descriptionl<n>_tx_error Input When asserted in an EOP cycle (while l<n>_tx_endofpacket is asserted), directs the IP

Related InformationAvalon Interface SpecificationsFor more information about the Avalon-ST interface.Low Latency 40-100GbE IP Core TX Data Bus Without

Signal Name Direction Descriptiondin_eop[<w>-1:0]Input End of packet location in the TX data bus. Indicates the 64-bit wordthat holds the end-of

Figure 3-7: Reduced Bandwidth With Left-Aligned SOP RequirementIllustrates the reduction of bandwidth that would be caused by left-aligning the SOP fo

For example, the destination MAC address includes the following six octets AC-DE-48-00-00-80. The firstoctet transmitted (octet 0 of the MAC address d

Figure 3-10: Byte Order on the Avalon-ST Interface Lanes With Preamble Pass‑ThroughDescribes the byte order on the Avalon-ST interface when the preamb

As illustrated, on the MAC client side you can choose a wide, standard Avalon® Streaming (Avalon-ST)interface, or a narrower, custom streaming interfa

Figure 3-11: Octet Transmission on the Avalon-ST Signals With Preamble Pass-ThroughIllustrates how the octets of the client frame are transferred over

Low Latency 40-100GbE IP Core RX DatapathThe Low Latency 40-100GbE RX MAC receives Ethernet frames from the PHY and forwards the payloadwith relevant

Low Latency 40-100GbE IP Core RX FilteringThe Low Latency 40-100GbE IP core processes all incoming valid frames. However, the IP core does notforward

character when it expects a terminate character. The Low Latency 40-100GbE IP core detects and handlesthe following forms of malformed packets:• If th

Control Frame IdentificationThe mechanisms to process flow control frames from the Ethernet link are specific to the flow controlmode of the LL 40-100

Low Latency 40-100GbE IP Core RX Data BusThe Low Latency 40-100GbE IP core RX datapath employs the Avalon-ST protocol. The Avalon-STprotocol is a sync

Name Direction Descriptionl<n>_rx_error[5:0] Output Reports certain types of errors in the Ethernet framewhose contents are currently being tran

Name Direction Descriptionl<n>_rx_fcs_errorOutput When asserted, indicates an FCS error condition. The IPcore asserts the l<n>_rx_fcs_erro

Figure 3-15: Traffic on the TX and RX Avalon-ST Client Interface for Low Latency 40GbE IP CoreShows typical traffic for the TX and RX Avalon-ST interf

Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)The RX bus without adapters consists of four 8-byte words, or 2

• Optional custom streaming data path interface with narrower bus width and a start frame possible on64-bit word boundaries without the optional adapt

Signal Name Direction Descriptiondout_eop[<w>–1:0]Output Indicates the final word of a frame in the current clk_rxmac cycle. IfCRC removal is di

Signal Name Direction Descriptionrx_fcs_errorOutput The current or most recent EOP byte is part of a frame with anincorrect FCS (CRC-32) value. By def

Related Information• Low Latency 40-100GbE IP Core MAC Configuration Registers on page 3-83Describes the MAX_RX_SIZE_CONFIG and CFG_PLEN_CHECK registe

The port is expected to receive the clock from the external TX MAC PLL and drives the internal clockclk_txmac. The required TX MAC clock frequency is

Figure 3-18: The XOFF and XON Pause Frames for Standard Flow ControlXOFF Frame XON FrameSTART[7:0] START[7:0]PREAMBLE[47:0] PREAMBLE[47:0]SFD[7:0] SFD

Conditions Triggering XOFF Frame TransmissionThe LL 40-100GbE IP core supports retransmission. In retransmission mode, the IP core retransmits aXOFF f

Table 3-7: Pause Control and Generation SignalsDescribes the signals that implement pause control. These signals are available only if you turn on flo

• Processing—You can enable or disable pause frame processing. If you disable pause frame processing,the IP core does not modify its behavior in respo

If you turn on bit [1] of the LINK_FAULT_CONFIG register, the IP core conforms to Clause 66 of the IEEE802.3-2012 Ethernet Standard and transmits the

Signal Name Direction Descriptionlink_fault_gen_en Output The IP core asserts this signal if the PCS is enabled to generate aremote fault sequence on

Low Latency 40-100GbE IP Core Device Family and Speed Grade SupportThe following sections list the device family and device speed grade support offere

Name SignalDirectionDescriptiontx_inc_maxOutput Asserted for one cycle when a maximum-size TX frame is transmitted.You program the maximum number of b

Name SignalDirectionDescriptiontx_inc_sizeok_fcserrOutput Asserted for one cycle when a valid TX frame with FCS errors istransmitted.RX Statistics Cou

Name SignalDirectionDescriptionrx_inc_ucast_data_okOutput Asserted for one cycle when a valid unicast RX frame, excludingcontrol frames, is received.r

cumulative count of the payload bytes in the qualifying transmitted frames, and complies with section5.2.2.18 of the IEEE Standard 802.3-2008.To suppo

• 1588 PTP Registers on page 3-103• IEEE websiteThe IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and ControlSyste

Figure 3-20: Example Ethernet System with Ordinary Clock Master and Ordinary Clock SlaveYou can implement both master and slave clocks using the Alter

Figure 3-22: Software Flow Using Transparent Clock Mode SystemThis figure from the 1588 standard is augmented with the timestamp labels shown in the t

Figure 3-23: Example Boundary Clock with One Slave Port and Two Master PortsYou can implement a 1588 system in boundary clock mode using the LL 40-100

Figure 3-24: PTP Receive Block DiagramRXAdapterRXPCSRX MACPTP_RXTOD Modulerx_dataSoPRX PMASOPtod_rxmac_inrx_todclk_rxmacRelated InformationIEEE websit

Figure 3-25: PTP Transmit Block DiagramTXAdapterTXPCSTXPMATX PTPTOD ModuleTX MACtx_dataptp_datatod_txmac_in clk_txmacptp_pkt_outtod_tx_clk_st2If the I

Low Latency 40-100GbE IP Core Device Speed Grade SupportTable 1-3: Slowest Supported Device Speed GradesLists the slowest supported device speed grade

External Time-of-Day Module for 1588 PTP VariationsLow Latency 40-100GbE IP cores that include the 1588 PTP module require an external time-of-day(TOD

Signal Name Direction Descriptiontx_in_ptp_overwrite[1:0]Input If the current packet is a 1588 PTP packet, indicates to the TXMAC what it should do to

Signal Name Direction Descriptiontx_in_zero_tcp Input New signal in 14.1 release. The TX client asserts this signal duringa TX SOP cycle to tell the I

If the value in the ptp_v2 field of the TX_PTP_STATUS register has the value of 0, the IP core outputstimestamps in the V1 format in the lower 64 bits

The IP core includes the option to implement the following features:• KR auto-negotiation provides a process to explore coordination with a link partn

Signal Name Direction Descriptionstatus_write Input Write commandstatus_writedata [31:0] Input Data to be writtenstatus_readdata [31:0] Output Read da

Arria 10 Transceiver Reconfiguration InterfaceArria 10 variations provide a dedicated Avalon-MM interface, called the Arria 10 transceiver reconfigura

322.265625 MHz ± 100 ppm. The ±100ppm value is required for any clock source providing thetransceiver reference clock.Sync–E IP core variations are IP

Signal Name Descriptiontx_serial_clk[3:0] (for40GbE and CAUI-4 variationsthat target an Arria 10 device)tx_serial_clk[9:0] (forstandard 100GbE variati

Figure 3-27: Clock Generation CircuitryProvides a high-level view of the clock generation circuitry and clock distribution to the transceiver. InArria