Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 103)

Signal Name Direction Interface

din_eop[<w>-1:0]

Each IP core instance has

Avalon-ST TX and RX client

interfaces, or custom streaming

TX and RX client interfaces.

Input

din_eop_empty[<w>*3-1:0]

Input

din_idle[<w>-1:0]

Input

din_req Output

tx_error[<w>-1:0] Input

clk_rxmac

Output Clocks

RX client interface

l<n>_rx_data[<n>*64-1:0]

Output

Avalon-ST RX client interface

Each IP core instance has

Avalon-ST TX and RX client

interfaces, or custom streaming

TX and RX client interfaces.

l<n>_rx_empty[<l>-1:0]

Output

l<n>_rx_startofpacket

Output

l<n>_rx_endofpacket

Output

l<n>_rx_error[5:0]

Output

l<n>_rx_valid

Output

l<n>_rx_fcs_valid

Output

l<n>_rx_fcs_error

Output

l<n>_rx_status[2:0] Output

dout_d[<w>*64-1:0]

Output

Custom streaming RX client

interface

Each IP core instance has

Avalon-ST TX and RX client

interfaces, or custom streaming

TX and RX client interfaces.

dout_c[<w>*8-1:0]

Output

dout_sop[<w>-1:0]

Output

dout_eop[<w>–1:0]

Output

dout_eop_empty[<w>*3-1:0]

Output

dout_idle[<w>-1:0] Output

rx_error[5:0] Output

rx_fcs_error

Output

rx_fcs_valid

Output

3-58

Low Latency 40-100GbE IP Core Signals

UG-01172

2015.05.04

Altera Corporation

Functional Description

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