Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 163)

Word Addr Bit R/W Name Description

0x4B1

R SEQ Link Ready When asserted, the sequencer is indicating that the

link is ready.

1 R SEQ AN timeout When asserted, the sequencer has had an Auto

Negotiation timeout. This bit is latched and is reset

when the sequencer restarts Auto Negotiation.

2 R SEQ LT timeout When set, indicates that the Sequencer has had a

timeout.

13:8 R SEQ Reconfig

Mode[5:0]

Specifies the Sequencer mode for PCS reconfigura‐

tion. The following modes are defined:

• Bit 8, mode[0]: AN mode

• Bit 9, mode[1]: LT Mode

• Bit 10, mode[2]: 10G data mode

• Bit 11, mode[3]: Gige data mode

• Bit 12, mode[4]: Reserved for XAUI

• Bit 13, mode[5]: 10G FEC mode

16 R KR FEC ability

170.0

When set to 1, indicates that the 10GBASE-KR

PHY supports FEC. Set as parameter SYNTH_FEC.

For more information, refer to Clause 45.2.1.84 of

IEEE 802.3ap-2007.

17 R KR FEC err ind

ability 170.0

When set to 1, indicates that the 10GBASE-KR

PHY is capable of reporting FEC decoding errors

to the PCS. For more information, refer to Clause

74.8.3 of IEEE 802.3ap-2007.

0x4B2

0:10 — Reserved —

11 RW KR FEC TX Error

Insert

Writing a 1 inserts one error pulse into the TX FEC

depending on the Transcoder and Burst error

settings. This bit self clears.

31:12 — Reserved —

0x4B5 to

0x4BF

Reserved for 40G KR Intentionally left empty for address compatibility

with 40G MAC + PHY KR solutions.

B-4

10GBASE-KR PHY Register Definitions

UG-01172

2015.05.04

Altera Corporation

Arria 10 10GBASE-KR Registers

Send Feedback

1 2 ... 158 159 160 161 162 163 164 165 166 167 168 ... 195 196

Kommentare zu diesen Handbüchern

Keine Kommentare

Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 163

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Messgeräte Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore