Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 22
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Parameter Type Range Default Setting Parameter Description
Enable TX
CRC insertion
Boolean • True
• False
True If turned on, the IP core inserts a
32-bit Frame Check Sequence (FCS)
, which is a CRC-32 checksum, in
outgoing Ethernet frames. If turned
off, the IP core does not insert the
CRC-32 sequence in outgoing
Ethernet communication. Turning
on TX CRC insertion improves
reliability but increases resource
utilization and latency through the
IP core.
If you turn on flow control, the IP
core must be configured with TX
CRC insertion, and this parameter is
not available.
Enable
preamble
passthrough
Boolean • True
• False
False If turned on, the IP core is in RX
and TX preamble pass-through
mode. In RX preamble pass-through
mode, the IP core passes the
preamble and SFD to the client
instead of stripping them out of the
Ethernet packet. In TX preamble
pass-through mode, the client
specifies the preamble to be sent in
the Ethernet frame.
Enable
alignment
EOP on FCS
word
Boolean • True
• False
True If turned on, the IP core aligns the
32-bit Frame Check Sequence (FCS)
error signal with the assertion of the
EOP by delaying the RX data bus to
match the latency of the FCS
computation. If turned off, the IP
core does not delay the RX data bus
to match the latency of the FCS
computation. If the parameter is
turned off, the FCS error signal, in
the case of an FCS error, is asserted
in a later clock cycle than the
relevant assertion of the EOP signal.
You must turn on this parameter if
your design relies on the rx_inc_
octetsOK signal..
2-8
IP Core Parameters
UG-01172
2015.05.04
Altera Corporation
Getting Started
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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