Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 156)

Figure A-2: High Level Block Diagram for the Arria 10 40-100GbE CAUI-4 Legacy Example Project

The non-device configurable example project for CAUI-4 variations configures two ATX PLLs and

connects the output tx_serial_clk signal of each ATX PLL to two of the four IP core transceiver

channels. The required ATX PLL output frequency only supports a fanout of two. If this arrangement is

not available for your design, you can use additional external ATX and CMU PLLs to generate and

distribute the tx_serial_clk signals for the individual channels. This project is a legacy project; it can be

compiled for static timing and resource utilization information, but is not configurable in hardware.

Altera does not yet provide a configurable example project for the CAUI-4 IP core.

Low Latency 40- or 100-Gbps Ethernet Example Project for CAUI-4 Arria 10 IP Core Variations

Altera FPGA

ATX

PLL

pll_locked

tx_serial_clk[3:0]

ATX

PLL

Low latency 40- or 100-Gbps Ethernet MAC and PHY

MegaCore Function

FIFO

MAC

Transceiver PHY

Avalon-ST

Control and

Status Interface

Avalon-MM

Arria 10 Transceiver

Reconfiguration

Interface

UG-01172

2015.05.04

Connections in the Low Latency 40-100GbE IP Core Example Project

A-3

Low Latency 40-100GbE IP Core Example Project

Altera Corporation

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Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 156