Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 115
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Addr Name Bit Description HW Reset
Value
Access
0x340 PHY_REFCLK_
KHZ
[31:0] Reference clock frequency in KHz, assuming
the clk_status clock has the frequency of
100 MHz. The reference clock frequency is
the value in the PHY_REFCLK_KHZ register
times the frequency of the clk_status clock,
divided by 100.
RO
0x341 PHY_RXCLK_
KHZ
[31:0] RX clock (clk_rxmac) frequency in KHz,
assuming the clk_status clock has the
frequency of 100 MHz. The RX clock
frequency is the value in the PHY_REFCLK_KHZ
register times the frequency of the clk_
status clock, divided by 100.
RO
0x342 PHY_TXCLK_
KHZ
[31:0] TX clock (clk_txmac) frequency in KHz,
assuming the clk_status clock has the
frequency of 100 MHz. The TX clock
frequency is the value in the PHY_REFCLK_KHZ
register times the frequency of the clk_
status clock, divided by 100.
RO
0x343 PHY_RECCLK_
KHZ
[31:0] RX recovered clock frequency in KHz,
assuming the clk_status clock has the
frequency of 100 MHz. The RX recovered
clock frequency is the value in the PHY_
REFCLK_KHZ register times the frequency of
the clk_status clock, divided by 100.
RO
0x344 PHY_
TXIOCLK_KHZ
[31:0] TX PMA clock frequency in KHz, assuming
the clk_status clock has the frequency of
100 MHz. The TX PMA clock frequency is
the value in the PHY_REFCLK_KHZ register
times the frequency of the clk_status clock,
divided by 100.
RO
Link Fault Signaling Registers
Table 3-21: LINK_FAULT_CONFIG Register—Offset 0x405
Name Bit Description
Reset
Value
Access
Unidir Enable [1]
When asserted, the IP core includes Clause 66 support for
remote link fault reporting on the Ethernet link.
1'b0
RW
Link Fault
Reporting
Enable
[0]
When asserted, the PCS generates remote fault sequence
on the Ethernet link, if conditions are met.
1’b1 RW
3-70
Link Fault Signaling Registers
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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