Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 140
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Address Name- Description Access
0x818 CNTR_TX_
65to127B_LO
Number of transmitted frames between 65–127 bytes (lower
32 bits)
RO
0x819 CNTR_TX_
65to127B_HI
Number of transmitted frames between 65–127 bytes
(upper 32 bits)
RO
0x81A CNTR_TX_
128to255B_LO
Number of transmitted frames between 128 –255 bytes
(lower 32 bits)
RO
0x81B CNTR_TX_
128to255B_HI
Number of transmitted frames between 128 –255 bytes
(upper 32 bits)
RO
0x81C CNTR_TX_
256to511B_LO
Number of transmitted frames between 256 –511 bytes
(lower 32 bits)
RO
0x81D CNTR_TX_
256to511B_HI
Number of transmitted frames between 256 –511 bytes
(upper 32 bits)
RO
0x81E CNTR_TX_
512to1023B_LO
Number of transmitted frames between 512–1023 bytes
(lower 32 bits)
RO
0x81F CNTR_TX_
512to1023B_HI
Number of transmitted frames between 512 –1023 bytes
(upper 32 bits)
RO
0x820 CNTR_TX_
1024to1518B_LO
Number of transmitted frames between 1024–1518 bytes
(lower 32 bits)
RO
0x821 CNTR_TX_
1024to1518B_HI
Number of transmitted frames between 1024–1518 bytes
(upper 32 bits)
RO
0x822 CNTR_TX_
1519toMAXB_LO
Number of transmitted frames of size between 1519 bytes
and the number of bytes specified in the MAX_TX_SIZE_
CONFIG register (lower 32 bits)
RO
0x823 CNTR_TX_
1519toMAXB_HI
Number of transmitted frames of siz between 1519 bytes
and the number of bytes specified in the MAX_TX_SIZE_
CONFIG register (upper 32 bits)
RO
0x824 CNTR_TX_
OVERSIZE_LO
Number of oversized frames (frames with more bytes than
the number specified in the MAX_TX_SIZE_CONFIG register)
transmitted (lower 32 bits)
RO
0x825 CNTR_TX_
OVERSIZE_HI
Number of oversized frames (frames with more bytes than
the number specified in the MAX_TX_SIZE_CONFIG register)
transmitted (upper 32 bits)
RO
0x826 CNTR_TX_MCAST_
DATA_OK_LO
Number of valid multicast frames transmitted, excluding
control frames (lower 32 bits)
RO
UG-01172
2015.05.04
TX Statistics Registers
3-95
Functional Description
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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