Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 41)

Simulating the Low Latency 40‑100GbE IP Core With the Testbenches

You can simulate the Low Latency 40-100GbE IP core using the Altera-supported versions of the Mentor

Graphics ModelSim SE, Cadence NCSim, and Synopsys VCS simulators for the current version of the

Quartus II software. The ModelSim-AE simulator does not have the capacity to simulate this IP core.

The example testbenches simulate packet traffic at the digital level. The testbenches do not require special

SystemVerilog class libraries.

The top-level testbench file for non-40GBASE-KR4 variations consists of a simple packet generator and

checker and one IP core in a loopback configuration.

The top-level testbench file for 40GBASE-KR4 variations consists of a symmetric arrangement with two

IP cores and traffic between them. For each IP core there is a packet generator to send traffic on the TX

side of the IP core and a packet checker to check the packets it receives from the other IP core. The two IP

cores communicate with each other through their Ethernet link, in which the testbench injects random

skew. The 40GBASE-KR4 testbench connects each IP core to a transceiver TX PLL, and exercises auto-

negotiation, link training, and data mode.

The example testbenches contain the test files and run scripts for the ModelSim, Cadence, and Synopsys

simulators. The run scripts use the file lists in the wrapper files. When you launch a simulation from the

original directory, the relative filenames in the wrapper files allow the run script to locate the files

correctly. When you generate the testbench for a Low Latency 40-100GbE IP core that targets an Arria 10

device, the software generates a copy of the IP core variation with a specific relative path from the

testbench scripts.

The following sections provide directions for generating the testbench and running tests with the

ModelSim, Cadence, and Synopsys simulators.

Generating the Low Latency 40-100GbE Testbench on page 2-28

Optimizing the Low Latency 40-100GbE IP Core Simulation With the Testbenches on page 2-29

Simulating with the Modelsim Simulator on page 2-29

Simulating with the NCSim Simulator on page 2-30

Simulating with the VCS Simulator on page 2-30

Testbench Output Example: Low Latency 40-100GbE IP Core on page 2-30

UG-01172

2015.05.04

Simulating the Low Latency 40‑100GbE IP Core With the Testbenches

2-27

Getting Started

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1800MX	Spécifications Maxum 1800MX Specifications, 96 pages
2400 SC3	Spécifications Maxum 2400 SC3 Specifications, 56 pages

Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 41