Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 65
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Low Latency 40-100GbE IP Core RX Data Bus
The Low Latency 40-100GbE IP core RX datapath employs the Avalon-ST protocol. The Avalon-ST
protocol is a synchronous point-to-point, unidirectional interface that connects the producer of a data
stream (source) to a consumer of data (sink). The key properties of this interface include:
• Start of packet (SOP) and end of packet (EOP) signals delimit frame transfers.
• A valid signal qualifies signals from source to sink.
Altera provides an Avalon-ST interface for both the LL 40GbE and LL 100GbE IP cores. In the 40GbE IP
core, the interface width is 256 bits, and in the 100GbE IP core, the interface width is 512 bits. In the LL
40GbE IP core, the client interface operates at a frequency of 312.5 MHz, and in the LL 100GbE IP core,
the client interface operates at a frequency of 390.625 MHz. The Avalon-ST interface requires that the
start of packet (SOP) always be in the MSB.
The RX MAC acts as a source and the client acts as a sink in the receive direction.
Figure 3-14: RX MAC to Client Interface
The Avalon-ST interface bus width varies with the IP core variation. In the figure, <n> = 4 for the 40GbE
IP core and <n> = 8 for the 100GbE IP core. <l> is log
2
(8*<n>).
l<n>_rx_data[<n>*64-1:0]
l<n>_rx_empty[<l>-1:0]
l<n>_rx_startofpacket
l<n>_rx_endofpacket
l<n>_rx_error[5:0]
l<n>_rx_valid
l<n>_rx_fcs_valid
l<n>_rx_fcs_error
l<n>_rx_status[2:0]
RX
Client
RX
MAC
Table 3-5: Signals of the RX Client Interface
In the table, <n> = 4 for the 40GbE IP core and <n> = 8 for the 100GbE IP core. <l> is log
2
(8*<n>). The signals
are clocked by clk_rxmac.
Name Direction Description
l<n>_rx_data[<n>*64-1:0]
Output RX data.
l<n>_rx_empty[<l>-1:0]
Output Indicates the number of empty bytes on l<n>_rx_data
when l<n>_rx_endofpacket is asserted, starting from the
least significant byte (LSB).
l<n>_rx_startofpacket
Output When asserted, indicates the start of a packet. The packet
starts on the MSB.
l<n>_rx_endofpacket
Output When asserted, indicates the end of packet.
3-20
Low Latency 40-100GbE IP Core RX Data Bus
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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