Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 66
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Name Direction Description
l<n>_rx_error[5:0] Output Reports certain types of errors in the Ethernet frame
whose contents are currently being transmitted on the
client interface. This signal is valid in EOP cycles only. To
ensure you can identify the corresponding packet, you
must turn on Enable alignment EOP on FCS word in the
LL 40-100GbE parameter editor.
The individual bits report different types of errors:
• Bit [0]: Malformed packet error. If this bit has the value
of 1, the packet is malformed. The IP core identifies a
malformed packet when it receives a control character
that is not a terminate character, while receiving the
packet.
• Bit [1]: CRC error. If this bit has the value of 1, the IP
core detected a CRC error in the frame.
If you turn on Enable alignment EOP on FCS word,
this bit and the l<n>_rx_fcs_error signal behave
identically.
• Bit [2]: undersized payload. If this bit has the value of
1, the frame size is between nine and 63 bytes,
inclusive. The IP core does not recognize an incoming
frame of size eight bytes or less as a frame, and those
cases are not reported here.The l<n>_rx_error[1] or
rx_error[1] also signals an FCS error.
• Bit [3]: oversized payload. If this bit has the value of 1,
the frame size is greater than the maximum frame size
programmed in the MAX_RX_SIZE_CONFIG register at
offset 0x506.
• Bit [4]: payload length error. If this bit has the value of
1, the payload received in the frame did not match the
length field value, and the value in the length field is
less than 1536 bytes. This bit only reports errors if you
set bit [0] of the CFG_PLEN_CHECK register at offset
0x50A to the value of 1.
• Bit [5} Reserved.
l<n>_rx_valid
Output When asserted, indicates that RX data is valid. Only valid
between the l<n>_rx_startofpacket and l<n>_rx_
endofpacket signals.
l<n>_rx_fcs_valid
Output When asserted, indicates that FCS is valid.
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core RX Data Bus
3-21
Functional Description
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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