Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 31)

File Name Description

<my_ip>.regmap If IP contains register information, .regmap file generates.

The .regmap file describes the register map information of master

and slave interfaces. This file complements the .sopcinfo file by

providing more detailed register information about the system. This

enables register display views and user customizable statistics in the

System Console.

<my_ip>.svd

Allows HPS System Debug tools to view the register maps of

peripherals connected to HPS within a Qsys system.

During synthesis, the .svd files for slave interfaces visible to System

Console masters are stored in the .sof file in the debug section.

System Console reads this section, which Qsys can query for register

map information. For system slaves, Qsys can access the registers by

name.

<my_ip>.v

<my_ip>.vhd

HDL files that instantiate each submodule or child IP core for

synthesis or simulation.

mentor/

Contains a ModelSim

script msim_setup.tcl to set up and run a

simulation.

aldec/

Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a

simulation.

/synopsys/vcs

/synopsys/vcsmx

Contains a shell script vcs_setup.sh to set up and run a VCS

simulation.

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to

set up and run a VCS MX

simulation.

/cadence

Contains a shell script ncsim_setup.sh and other setup files to set up

and run an NCSIM simulation.

/submodules Contains HDL files for the IP core submodule.

<child IP cores>/ For each generated child IP core directory, Qsys generates /synth and /

sim sub-directories.

Integrating Your IP Core in Your Design

When you integrate your IP core instance in your design, you must pay attention to the following items:

Pin Assignments on page 2-18

External Transceiver Reconfiguration Controller Required in Stratix V Designs on page 2-18

External Transceiver PLL Required in Arria 10 Designs on page 2-19

External Time-of-Day Module for Variations with 1588 PTP Feature on page 2-20

UG-01172

2015.05.04

Integrating Your IP Core in Your Design

2-17

Getting Started

Altera Corporation

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