Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 108
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reconfig_clk
Input Clocks
Arria 10 Native PHY IP core
reconfiguration interface
This signal is available in Arria
10 devices only.
reconfig_reset
Input Resets
Arria 10 Native PHY IP core
reconfiguration interface
This signal is available in Arria
10 devices only.
reconfig_address [11:0]
(40GbE and CAUI-4)
reconfig_address [13:0]
(100GbE)
Input
Arria 10 Native PHY IP core
reconfiguration interface
These signals are available in
Arria 10 devices only.
reconfig_read
Input
reconfig_write
Input
reconfig_writedata[31:0]
Input
reconfig_readdata[31:0]
Output
reconfig_waitrequest
Output
pll_locked
Input
External transceiver PLL
interface. These signals are
available in Arria 10 devices
only.
tx_serial_clk[3:0] (40GbE
and CAUI–4)
tx_serial_clk[9:0] (100GbE)
Input
Related Information
• Clocks on page 3-51
Overview of IP core clocks. Includes list of clock signals and recommended and required frequencies.
• Resets on page 3-54
• Transceiver PHY Serial Data Interface on page 3-48
• PHY Status Interface on page 3-48
• Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) on page 3-7
Describes the TX client interface.
• Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) on
page 3-10
• Low Latency 40-100GbE IP Core RX Data Bus on page 3-20
Describes the RX client interface.
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core Signals
3-63
Functional Description
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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