Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 142
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Address Name- Description Access
0x836 CNTR_TX_ST_LO Number of transmitted frame starts (lower 32 bits) RO
0x837 CNTR_TX_ST_HI Number of transmitted frame starts (upper 32 bits) RO
0x838–
0x83F
Reserved
0x840 TXSTAT_REVID TX statistics module revision ID. RO
0x841 TXSTAT_SCRATCH Scratch register available for testing. Default value is 0x08. RW
0x842 TXSTAT_NAME_0 First 4 characters of IP core variation identifier string
"040gMacStats" or "100gMacStats"
RO
0x843 TXSTAT_NAME_1 Next 4 characters of IP core variation identifier string
"040gMacStats" or "100gMacStats"
RO
0x844 TXSTAT_NAME_2 Final 4 characters of IP core variation identifier string
"040gMacStats" or "100gMacStats"
RO
0x845
CNTR_TX_CONFIG Bits [2:0]: Configuration of TX statistics counters:
• Bit [2]: Shadow request (active high): When set to the
value of 1, TX statistics collection is paused. The
underlying counters continue to operate, but the
readable values reflect a snapshot at the time the pause
flag was activated. Write a 0 to release.
• Bit [1]: Parity-error clear. When software sets this bit,
the IP core clears the parity bit CNTR_TX_STATUS[0].
This bit (CNTR_TX_CONFIG[1]) is self-clearing.
• Bit [0]: Software can set this bit to the value of 1 to reset
all of the TX statistics registers at the same time. This bit
is self-clearing.
Bits [31:3] are Reserved.
RW
0x846
CNTR_TX_STATUS • Bit [1]: Indicates that the TX statistics registers are
paused (while CNTR_TX_CONFIG[2] is asserted) .
• Bit [0]: Indicates the presence of at least one parity error
in the TX statistics counters.
Bits [31:2] are Reserved.
RO
0x860 TxOctetsOK_LO Number of transmitted payload bytes in frames with no
FCS, undersized, oversized, or payload length errors. This
register is compliant with section 5.2.2.18 of the IEEE
Standard 802.3-2008.
Instead of an increment vector, this register corresponds to
the signals tx_inc_octetsOK[15:0] and tx_inc_
octetsOK_valid.
RO
0x861 TxOctetsOK_HI RO
UG-01172
2015.05.04
TX Statistics Registers
3-97
Functional Description
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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