Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 186)

Property Low Latency 40-100GbE IP Core 40-100GbE IP Core v14.0

Reset Single asynchronous reset signal

resets the entire IP core. Additional

reset signals reset the individual

Avalon-MM interfaces: the control

and status interface in all IP core

variations, and the Arria 10

transceiver reconfiguration interface

in IP core variations that target an

Arria 10 device.

Five asynchronous reset signals

reset individual components of

the IP core. User must enforce

recommended reset sequence.

Clocks Input clocks for Avalon-MM

interfaces and PLL reference clock.

PLL reference clock drives internal

IP core clocks, and clk_rxmac and

clk_txmac are output clocks.

Configurable option to provide TX

MAC input clock from an external

PLL or to include the PLL in the IP

core. Clock signal from the external

MAC PLL is a new input clock

signal.

Input clocks for Avalon-MM

interfaces, PLL reference clock,

and RX and TX MAC (clk_

rxmac and clk_txmac).

Stratix V transceiver dynamic

reconfiguration controller

You must instantiate an external

reconfiguration controller.

You must instantiate an external

reconfiguration controller.

TX error insertion test and

debug feature

Available Not available

RX control frame status flags Available Not available

Related Information

Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision

History on page 8-1

For information about the changes to the Low Latency 40-100GbE MegaCore function in the different

software releases.

40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

For detailed information about changes to top-level interfaces in different versions of the legacy

40-100GbE IP core, refer to the Document Revision History in the Additional Information chapter.

MegaCore IP Library Release Notes and Errata

For information about changes in different versions of the legacy 40-100GbE IP core, refer to the Product

Revision History in the 40-100GbE MegaCore function chapter. The Low Latency 40-100GbE IP core

v14.0 is an extended IP core. Extended IP cores are not included in this document. The Low Latency

40-100GbE IP core is documented in the Altera IP Release Notes starting in version 14.0 Arria 10 Edition.

UG-01172

2015.05.04

Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.0

C-5

Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.0

Altera Corporation

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