Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 89
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Figure 3-25: PTP Transmit Block Diagram
TX
Adapter
TX
PCS
TX
PMA
TX PTP
TOD Module
TX MAC
tx_data
ptp_data
tod_txmac_in clk_txmac
ptp_pkt_out
tod_tx_clk_st2
If the IP core 1588 PTP module is in one-step mode, you must specify the offset of the timestamp in the
packet (tx_in_ptp_offset[15:0]), and provide an overwrite flag (tx_in_ptp_overwrite[1:0]) to tell
the IP core how to process the timestamp.
In one-step mode, the IP core either overwrites the timestamp information provided at the user-specified
offset with the packet exit timestamp, or adds the packet exit timestamp to the value at the specified offset,
or subtracts the current value at the specified offset from the packet exit timestamp, depending on the
value of tx_in_ptp_overwrite[1:0]. In addition, the IP core zeroes out the TCP checksum depending
on the value of tx_in_zero_tcp.
In two-step mode, the IP core ignores the values on the tx_in_ptp_offset[15:0] and
tx_in_ptp_overwrite[1:0] signals. Instead of modifying the current timestamp in the packet, the IP
core transmits a two-step derived timestamp on the separate tod_tx_clk_st2[95:0] bus, when the IP
core begins transmitting the Ethernet frame. The value on the tod_tx_clk_st2[95:0] bus is the packet
exit timestamp. tod_tx_clk_st2[95:0] holds a valid value when the ptp_pkt_out signal is asserted.
When the IP core is in this mode, user logic is responsible for updating the TCP checksum.
In both one-step mode and two-step mode, the IP core calculates the packet exit timestamp:
exit timestamp = entry timestamp + IP core maintained expected latency + user-specified extra latency
• The expected latency through the IP core is a static value that is correct in most cases. The IP core
maintains this value internally.
• The IP core reads the user-specified extra latency from the TX_PTP_EXTRA_LATENCY register. This
option is provided for user flexibility.
Related Information
• 1588 PTP Registers on page 3-103
• IEEE website
The IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control
Systems Standard is available on the IEEE website.
3-44
PTP Transmit Functionality
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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