Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung PDF herunterladen (Seite 3)

Compiling the Full Design and Programming the FPGA....................................................................2-31

Initializing the IP Core..............................................................................................................................2-31

Functional Description....................................................................................... 3-1

High Level System Overview......................................................................................................................3-2

Low Latency 40-100GbE MAC and PHY Functional Description.......................................................3-2

Low Latency 40-100GbE IP Core TX Datapath...........................................................................3-3

Low Latency 40-100GbE IP Core TX Data Bus Interfaces.........................................................3-6

Low Latency 40-100GbE IP Core RX Datapath.........................................................................3-16

Low Latency 40-100GbE IP Core RX Data Bus Interface........................................................ 3-19

Low Latency 100GbE CAUI–4 PHY...........................................................................................3-27

External Reconfiguration Controller.......................................................................................... 3-27

External Transceiver PLL..............................................................................................................3-27

External TX MAC PLL..................................................................................................................3-27

Congestion and Flow Control Using Pause Frames................................................................. 3-28

Pause Control and Generation Interface....................................................................................3-30

Pause Control Frame Filtering.....................................................................................................3-31

Link Fault Signaling Interface......................................................................................................3-32

Statistics Counters Interface.........................................................................................................3-34

1588 Precision Time Protocol Interfaces....................................................................................3-38

PHY Status Interface..................................................................................................................... 3-48

Transceiver PHY Serial Data Interface.......................................................................................3-48

Low Latency 40GBASE-KR4 IP Core Variations......................................................................3-48

Control and Status Interface.........................................................................................................3-49

Arria 10 Transceiver Reconfiguration Interface........................................................................3-51

Clocks.............................................................................................................................................. 3-51

Resets............................................................................................................................................... 3-54

Signals..........................................................................................................................................................3-55

Low Latency 40-100GbE IP Core Signals...................................................................................3-55

Software Interface: Registers.................................................................................................................... 3-64

Low Latency 40-100GbE IP Core Registers................................................................................3-67

Ethernet Glossary.....................................................................................................................................3-105

Debugging the 40GbE and 100GbE Link............................................................4-1

Low Latency 40-100GbE IP Core Example Project............................................A-1

Connections in the Low Latency 40-100GbE IP Core Example Project.............................................A-2

Generating the Low Latency 40-100GbE Example Project...................................................................A-4

Compiling the Low Latency 40-100GbE IP Core Example Project.....................................................A-5

Arria 10 10GBASE-KR Registers........................................................................B-1

10GBASE-KR PHY Register Definitions................................................................................................. B-1

About The Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function

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