Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 79
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Signal Name Direction Description
link_fault_gen_en Output The IP core asserts this signal if the PCS is enabled to generate a
remote fault sequence on the Ethernet link when appropriate.
Connects to the Link Fault Reporting Enable field in bit [0] of
the LINK_FAULT_CONFIG register at offset 0x405.
This signal is clocked by clk_status.
If you turn off Enable link fault generation this signal is not
available.
Related Information
• Link Fault Signaling Registers on page 3-70
Information about the Link Fault Reporting Enable register and the Unidir Enable register.
• IEEE website
The IEEE 802.3ba –2010 100G Ethernet Standard and the IEEE 802.3 –2012 Ethernet Standard are
available on the IEEE website.
Statistics Counters Interface
The statistics counters modules are synthesis options that you select in the Low Latency 40-100GbE
parameter editor. However, the statistics status bit output vectors are provided whether you select the
statistics counters module option or not.
The increment vectors are brought to the top level as output ports.The increment vectors also function
internally as input ports to the control and status registers (CSR).
Table 3-9: Statistics Counters Increment Vectors
The TX statistics counter increment vectors are clocked by the clk_txmac clock, and the RX statistics counter
increment vectors are clocked by the clk_rxmac clock.
Name Signal
Direction
Description
TX Statistics Counter Increment Vectors
tx_inc_64
Output Asserted for one cycle when a 64-byte TX frame is transmitted.
tx_inc_127
Output Asserted for one cycle when a 65–127 byte TX frame is transmitted.
tx_inc_255
Output Asserted for one cycle when a 128–255 byte TX frame is transmitted.
tx_inc_511
Output Asserted for one cycle when a 256–511 byte TX frame is transmitted.
tx_inc_1023
Output Asserted for one cycle when a 512–1023 byte TX frame is transmitted.
tx_inc_1518
Output Asserted for one cycle when a 1024–1518 byte TX frame is transmitted.
3-34
Statistics Counters Interface
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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