Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 193
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Date Compatible ACDS
Version
Changes
• Corrected addresses of the following statistics registers:
• CNTR_TX_CRCERR registers from 0x804-0x805 to 0x806-0x807.
• CNTR_TX_FCS registers from 0x806-0x807 to 0x804-0x805
• CNTR_RX_CRCERR registers from 0x904-0x8905 to 0x906-0x907.
• CNTR_RX_FCS registers from 0x906-0x907 to 0x904-0x905
• Corrected direction of clk_txmac and clk_rxmac in table in Signals
section to Output.
• Added HW reset values for PHY registers that have them. All PHY
register listings except those for the identifier string registers and
the frequency registers now list a HW reset value.
• Added basic information to description of HI BER field of PHY_
RXPCS_STATUS register.
2014.04.28 13.1 Update 3
13.1 Arria 10
Edition Update 2
• Corrected presentation of resource utilization numbers for Stratix V
device family to clarify size of IP core without 1588 PTP module
• Renamed Pause Registers tables to Ethernet Flow Control (Pause
Functionality) Registers for consistency
• In Low Latency 40-100GbE IP Core Address Map table, clarified
that the 1588 PTP registers are only available if you turn on the
parameter to include the 1588 PTP module in your IP core instance.
The same information was already available in the table for other
registers that are only available if you turn on the associated
parameter.
• Fixed assorted typos (column width in TX MAC Configuration
Registers table, reset value widths of RX_PAUSE_DADDR0 register in
RX Ethernet Flow Control Registers table and of TX_PTP_CLOCK_
PERIOD register in TX 1588 PTP Registers table)
2014.04.11 13.1 Update 3
13.1 Arria 10
Edition Update 2
• Added resource utilization numbers for Stratix V device family.
• Corrected supported Stratix V device speed grade information for
Low Latency 100GbE IP cores.
• Added note to supported Stratix V device speed grade information
table clarifying that Quartus II seed sweeping might be required for
variations that include a 1588 PTP module to achieve a comfortable
timing margin.
UG-01172
2015.05.04
Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User
Guide Revision History
D-7
Additional Information
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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