Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Bedienungsanleitung Seite 114
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Addr Name Bit Description HW Reset
Value
Access
0x315 PHY_PCS_
INDIRECT_
DATA
[3:0]
or
[9:0]
PCS indirect data. To read a FIFO flag, set the
value in the PHY_PCS_INDIRECT_ADDR
register to indicate the flag you want to read.
After you set the specific flag indication in
the PHY_PCS_INDIRECT_ADDR register, each
bit [n] in the PHY_PCS_INDIRECT_DATA
register has the value of that FIFO flag for the
transceiver channel for lane [n].
This register has four valid bits [3:0] in LL
40GbE IP core variations, and ten valid bits
[9:0] in standard LL 100GbE IP core
variations. This register is not valid for
CAUI-4 variations.
TX full flags
RO
0x320 PHY_TX_PLL_
LOCKED
[9:0]
Each bit that is asserted indicates that the
corresponding lane TX PLL is locked.
10'b0 RO
0x321 PHY_
EIOFREQ_
LOCKED
[9:0] Each bit that is asserted indicates that the
corresponding lane RX CDR PLL is locked.
10'b0 RO
RO
0x322
PHY_TX_
COREPLL_
LOCKED
[2] RX PLL is locked.
3'b0 RO[1] TX PLL is locked.
[0] TX PCS is ready.
0x323 PHY_FRAME_
ERROR
[3:0]
or
[19:0]
Each bit that is asserted indicates that the
corresponding virtual lane has a frame error.
These bits are sticky. You clear them with the
PHY_SCLR_FRAME_ERROR register.
0xF or
0xFFFFF
RO
0x324
PHY_SCLR_
FRAME_ERROR
[0] Synchronous clear for PHY_FRAME_ERROR
register. Write the value of 1 to this register
to clear the PHY_FRAME_ERROR register.
1'b0 RW
0x325
PHY_EIO_
SFTRESET
[1] Set this bit to clear the RX FIFO.
2'b00 RW
[0] RX PCS reset: set this bit to reset the RX
PCS.
0x326 PHY_RXPCS_
STATUS
[1:0] Indicates the RX PCS is fully aligned and
ready to accept traffic.
• Bit [1]: HI BER status (bit error rate is
high according to Ethernet standard
definition)
• Bit [0]: RX PCS fully aligned status
0 RO
UG-01172
2015.05.04
PHY Registers
3-69
Functional Description
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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