Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 436)

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17–8 Chapter 17: Transceiver PHY Reset Controller IP Core

Timing Constraints for Reset Signals when Using Bonded PCS Channels

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Timing Constraints for Reset Signals when Using Bonded PCS Channels

For designs that use bonded TX PCS channels, the reset signal to all TX PCS channels

within a bonded group must meet a maximum skew tolerance. This skew tolerance is

one-half the TX parallel clock cycle.

You must provide a Synopsys Design Constraint (SDC) for the reset signals to

guarantee that your design meets timing. Example 17–1 shows the general form for

this constraint. If your design includes the Transceiver PHY Reset Controller IP Core

or the embedded reset controller, you can substitute your instance and interface

names for the generic names shown in Example 17–1.

In Example 17–1, you must make the following substitutions:

■ <IP_INSTANCE_NAME>—substitute the name of your reset controller IP instance

or PHY IP instance

■ <1/2 coreclk period in ps>—substitute the 1/2 the clock period of your design in

picoseconds

If your design has custom reset logic, replace the

*<IP_INSTANCE_NAME>*tx_digital_reset*r_reset with the source register for the

TX PCS reset signal,

tx_digital_reset

Altera believes that most designs will meet this maximum skew requirement without

this constraint; however, it cannot be guaranteed without including this constraint.

f For more information about the

set_max_skew

constraint, refer to the SDC and

TimeQuest API Reference Manual.

Example 17–1. SDC Constraint for TX Digital Reset When Bonded Clocks Are Used

set_max_skew -from *<IP_INSTANCE_NAME>*tx_digitalreset*r_reset -to *pld_pcs_interface*

<1/2 coreclk period in ps>

1 2 ... 431 432 433 434 435 436 437 438 439 440 441 ... 483 484

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