Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 244)

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101

12–6 Chapter 12: Stratix V Transceiver Native PHY IP Core

PMA Parameters

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

TX PMA Parameters

Table 12–4 describes the TX PMA options you can specify.

f For more information about the TX CMU, ATX, and fractional PLLs, refer to the

Stratix V PLLs section in Transceiver Architecture in Stratix V Devices.

Table 12–4. TX PMA Parameters

Parameter Range Description

Enable TX PLL dynamic

reconfiguration

On/Off

When you turn this option On, you can dynamically reconfigure

the PLL to use a different reference clock input. This option is

also required to simulate TX PLL reconfiguration. If you turn this

option On, the Quartus II Fitter prevents PLL merging by default;

however, you can specify merging using the

FORCE_MERGE_PLL

QSF assignments.

Use external TX PLL On/Off

When you turn this option On, the Native PHY does not include

TX PLLs. Instead, the Native PHY includes a top-level signal or

bus,

ext_pll_clk[<n>-1:0]

that you can connect to external

PLLs. If you plan to dynamically reconfigure.

Number of TX PLLs 1–4

Specifies the number of TX PLLs required. More than 1 PLL is

typically required if your design reconfigures channels to run at

multiple frequencies.

Main TX PLL logical index 0–3 Specifies the index of the TX PLL used in the initial configuration.

Number of TX PLL reference

clocks

1–5

Specifies the total number of reference clocks that are shared by

all of the PLLs.

1 2 ... 239 240 241 242 243 244 245 246 247 248 249 ... 483 484

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