Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 361)

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Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–7

PMA Parameters

November 2012 Altera Corporation Altera Transceiver PHY IP Core

User Guide

Table 15–8 lists the best- case latency for the LSB of the TX serializer for all supported

interface widths for the PMA Direct datapath.

Table 15–9 shows the bits used for all FPGA fabric to PMA interface widths.

Regardless of the FPGA Fabric Interface Width selected, all 80 bits are exposed for the

TX and RX parallel data ports. However, depending upon the interface width selected

not all bits on the bus will be active. Table 15–9 shows which bits are active for each

FPGA Fabric Interface Width selection. For example, if your interface is 16 bits, the

active bits on the bus are [17:0] and [7:0] of the 80 bit bus. The non-active bits are tied

to ground.

Table 15–8. Latency for TX Serialization in Cyclone V Devices

FPGA Fabric Interface Width Arria V Latency in UI

8 bits 43

10 bits 53

16 bits 67

20 bits 83

64 bits 131

80 bits 163

Table 15–9. Active Bits for Each Fabric Interface Width

FPGA Fabric Interface

Width

Bus Bits Used

8 bits [7:0]

10 bits [9:0]

16 bits {[17:10], [7:0]}

20 bits [19:0]

80 bits [79:0]

1 2 ... 356 357 358 359 360 361 362 363 364 365 366 ... 483 484

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