Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 248)

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12–10 Chapter 12: Stratix V Transceiver Native PHY IP Core

PMA Parameters

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Table 12–9 lists the best- case latency for the LSB of the TX serializer for all supported

interface widths for the PMA Direct datapath.

Table 12–10 shows the bits used for all FPGA fabric to PMA interface widths.

Regardless of the FPGA Fabric Interface Width selected, all 80 bits are exposed for the

TX and RX parallel data ports. However, depending upon the interface width selected

not all bits on the bus will be active. Table 12–10 shows which bits are active for each

FPGA Fabric Interface Width selection. For example, if your interface is 16 bits, the

active bits on the bus are [17:0] and [7:0] of the 80 bit bus. The non-active bits are tied

to ground.

20 bits 23

32 bits 35

40 bits 43

64 bits 99

80 bits 123

Table 12–9. Latency for TX Serialization in Stratix V Devices

FPGA Fabric Interface Width Stratix V Latency in UI

8 bits 44

10 bits 54

16 bits 68

20 bits 84

32 bits 100

40 bits 124

64 bits 132

80 bits 164

Table 12–10. Active Bits for Each Fabric Interface Width

FPGA Fabric Interface

Width

Bus Bits Used

8 bits [7:0]

10 bits [9:0]

16 bits {[17:10], [7:0]}

20 bits [19:0]

32 bits {[37:30], [27:20], [17:10], [7:0]}

40 bits [39:0]

64 bits {[77:70], [67:60], [57:50], [47:40], [37:30], [27:20], [17:10], [7:0]}

80 bits [79:0]

Table 12–8. Latency for RX Deserialization in Stratix V Devices (Part 2 of 2)

FPGA Fabric Interface Width Stratix V Latency in UI

1 2 ... 243 244 245 246 247 248 249 250 251 252 253 ... 483 484

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