Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 433)

Chapter 17: Transceiver PHY Reset Controller IP Core 17–5

Interfaces

November 2012 Altera Corporation Altera Transceiver PHY IP Core

User Guide

Interfaces

Figure 17–2 illustrates the top-level signals of the Transceiver PHY Reset Controller IP

Core. Many of the signals in Figure 17–2 become buses if you choose separate reset

controls. The variables in Figure 17–2 represent the following parameters:

■ <n>—The number of lanes

■ <p>—The number of PLLs

Use separate RX reset per channel On/Off

When On, each RX channel has a separate reset input. When

Off, uses a shared RX reset controller for all channels.

RX automatic reset recovery mode

Auto

Manual

Expose Port

Specifies the Transceiver PHY Reset Controller behavior

when the

pll_locked

signal is deasserted. The following

modes are available:

■ Auto: The associated

rx_digital_reset

controller

automatically resets whenever the

rx_is_lockedtodata

signal is deasserted.

■ Manual: The associated

rx_digital_reset

controller is

not reset when the

rx_is_lockedtodata

signal is

deasserted, allowing you to choose corrective action.

■ Expose Port: The

rx_manual

signal is a top-level signal of

the IP Core. If the core include separate reset control for

each RX channel, each RX channel uses its respective

rx_is_lockedtodata

signal for automatic reset control;

otherwise, the inputs are

AND

ed to provide internal status

for the shared reset controller.

rx_analogreset duration

1–999999999

Specifies the time in ns to continue to assert the

rx_analogreset

after the reset input and all other gating

conditions are removed. The value is rounded up to the

nearest clock cycle. The default value is 4000 ns.

rx_digitalreset duration

1–999999999

Specifies the time in ns to continue to assert the

rx_digitalreset

after the reset input and all other gating

conditions are removed. The value is rounded up to the

nearest clock cycle. The default value is 40 ns.

Table 17–3. General Options (Part 3 of 3)

Name Range Description

Figure 17–2. Top-Level Signals of the Transceiver PHY Reset Controller

pll_locked[<p>-1:0]

pll_select[<p>-1:0]

tx_cal_busy[<n>-1:0]

rx_cal_busy[<n>-1:0]

rx_is_lockedtodata[<n>-1:0]

tx_manual[<n>-1:0]

rx_manual[<n>-1:0]

clock

reset

Transceiver PHY Reset Controller Top-Level Signals

tx_digitalreset[<n>-1:0]

tx_analogreset[<n>-1:0]

tx_ready[<n>-1:0]

rx_digitalreset[<n>-1:0]

rx_analogreset[<n>-1:0]

rx_ready[<n>-1:0]

pll_powerdown[<p>-1:0]

PLL and

Calibration

Status

PLL Powerdown

TX and RX

Resets and Status

Clock

and Reset

PLL

Control

1 2 ... 428 429 430 431 432 433 434 435 436 437 438 ... 483 484

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