Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 318)

100

101

14–10 Chapter 14: Arria V GZ Transceiver Native PHY IP Core

PMA Parameters

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Table 14–11 shows the bits used for all FPGA fabric to PMA interface widths.

Regardless of the FPGA Fabric Interface Width selected, all 80 bits are exposed for the

TX and RX parallel data ports. However, depending upon the interface width selected

not all bits on the bus will be active. Table 14–11 shows which bits are active for each

FPGA Fabric Interface Width selection. For example, if your interface is 16 bits, the

active bits on the bus are [17:0] and [7:0] of the 80 bit bus. The non-active bits are tied

to ground.

Table 14–11. Active Bits for Each Fabric Interface Width

FPGA Fabric Interface

Width

Bus Bits Used

8 bits [7:0]

10 bits [9:0]

16 bits {[17:10], [7:0]}

20 bits [19:0]

32 bits {[37:30], [27:20], [17:10], [7:0]}

40 bits [39:0]

64 bits {[77:70], [67:60], [57:50], [47:40], [37:30], [27:20], [17:10], [7:0]}

80 bits [79:0]

1 2 ... 313 314 315 316 317 318 319 320 321 322 323 ... 483 484

Kommentare zu diesen Handbüchern

Keine Kommentare

Altera UG-01080 Betriebsanweisung Seite 318

Kommentare zu diesen Handbüchern