Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 145)

Chapter 7: Interlaken PHY IP Core 7–9

Avalon-ST RX Interface

November 2012 Altera Corporation Altera Transceiver PHY IP Core

User Guide

rx_parallel_data<n>[65]

Output

Indicates whether

rx_parallel_data<n>[63:0]

represents

control or data. When deasserted,

rx_parallel_data<n>[63:0]

is a data word. When asserted,

rx_paralleldata<n>[63:0]

is a

control word. This output is synchronous to the

rx_coreclkin

clock domain.

The value of header synchronization bits[65:64] of the Interlaken

word identify whether bits[63:0] are Framing Layer

Control/Burst/IDLE Word or a data word. The value 2’b10 indicating a

Framing Layer Control/Burst/IDLE Word is gray encoded to the value

1’b1 and

rx_parallel_data<n>[65]

is asserted by the Interlaken

Receive PCS. The value 2’b01 indicating data word is gray encoded

to the value 1’b0 and

rx_parallel_data<n>[65]

is deasserted by

the Interlaken Receive PCS. The Framing Layer Control Words

(Frame Sync, Scrambler State, Skip, and Diag) are not discarded but

are sent to the Interlaken MAC for multi-lane alignment and deskew

on the lanes.

rx_parallel_data<n>[66]

Output

This is an active-high synchronous status signal indicating that block

lock (frame synchronization) and frame lock (metaframe boundary

delineation) have been achieved. The Interlaken MAC must use this

signal to indicate that Metaframe synchronization has been achieved

for this lane. You must use this

rx_parallel_data[66]

as the

primary frame synchronization status flag and only use the optional

rx_parallel_data[70]

as the secondary frame synchronization

status flag. This output is synchronous to the rx_coreclkin clock

domain.

If the RX PCS FIFO reaches the empty state or is in an empty state,

rx_parallel_data<n>[66]

Block Lock and Frame Lock status

signals are deasserted in the next clock cycle.

rx_parallel_data<n>[70]

indicating metaframe lock and

rx_parallel_data<n>[69]

indicating that the first Interlaken

synchronization word alignment pattern has been received remain

asserted.

rx_parallel_data<n>[67]

Output When asserted, indicates an RX FIFO overflow error.

rx_parallel_data<n>[68]

Output

When asserted, indicates that the RX FIFO is partially empty and is

still accepting data from the frame synchronizer. This signal is

asserted when the RX FIFO fill level is below the

rx_fifo_pempty

threshold. This output is synchronous to the rx_coreclkin clock

domain. To prevent underflow, the Interlaken MAC should begin

reading from the RX FIFO when this signal is deasserted, indicating

sufficient FIFO contents (RX FIFO level above

rx_fifo_pempty

threshold). The MAC should continue to read the RX FIFO to prevent

overflow as long as this signal is not reasserted. You can assert a

FIFO flush using the

rx_fifo_clr<n>

when the receive FIFO

overflows. This output is synchronous to the

rx_clkout

clock

domain.

You can tie this signal's inverted logic to the

rx_dataout_bp<n>

receive FIFO read enable signal as the following assignment

statement illustrates:

assign rx_dataout_bp[0] =!(rx_parallel_data[68]);

Table 7–5. Avalon-ST RX Signals (Part 2 of 4)

Signal Name Direction Description

1 2 ... 140 141 142 143 144 145 146 147 148 149 150 ... 483 484

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