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1–4 Chapter 1: Introduction

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Transceiver Reconfiguration Controller

Altera

Transceiver Reconfiguration Controller dynamically reconfigures analog

settings in Arria V, Cyclone V, and Stratix V devices. Reconfiguration allows you to

compensate for variations due to process, voltage, and temperature (PVT) in 28-nm

devices. It is required for Arria V, Cyclone V, and Stratix V devices that include

transceivers. For more information about the Transceiver Reconfiguration Controller,

refer to Transceiver Reconfiguration Controller IP Core. The reset controller may be

included in the transceiver PHY as Figure 1–1 illustrates or be a separately

instantiated component as Figure 1–2 illustrates.

Transceiver PHY Reset Controller

The embedded reset controller ensures reliable transceiver link initialization. The

reset controller initializes both the TX and RX channels. You can disable the automatic

reset controller in the Custom, Low Latency Transceiver, and Deterministic Latency

PHYs. If you disable the embedded reset controller, the powerdown, analog and

digital reset signals for both the TX and RX channels are top-level ports of the

transceiver PHY. You can use these ports to design a custom reset sequence, or you

can use the Altera-provided Transceiver Reset Controller IP Core.

The Transceiver PHY Reset Controller IP Core handles all reset sequencing of the

transceiver to enable successful operation. Because the Transceiver PHY Reset

Controller IP is available in clear text, you can also modify it to meet your

requirements. For more information about the Transceiver PHY Reset Controller, refer

to Transceiver Reconfiguration Controller IP Core.

1 To accommodate different reset requirements for different transceivers in your design,

instantiate multiple instances of a PHY IP core. For example, if your design includes

20 channels of the Custom PHY IP core with 12 channels running a custom protocol

using the automatic reset controller and 8 channels requiring manual control of RX

reset, instantiate 2 instances of the Custom PHY IP core and customize one to use

automatic mode and the other to use your own reset logic. For more information, refer

to “Enable embedded reset control” in Custom PHY General Options.

f For more information about reset control in Stratix V devices, refer to Transceiver Reset

Control in Stratix V Devices in volume 3 of the Stratix V Device Handbook. For Stratix IV

devices, refer to Reset Control and Power Down in volume 4 of the Stratix IV Device

Handbook. For Arria V devices, refer to Transceiver Reset Control and Power-Down in

Arria V Devices. For Cyclone V devices refer to Transceiver Reset Control and Power

Down in Cyclone V Devices.

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