Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 143)

Chapter 7: Interlaken PHY IP Core 7–7

Avalon-ST TX Interface

November 2012 Altera Corporation Altera Transceiver PHY IP Core

User Guide

tx_ready

Output

When asserted, indicates that the TX interface has exited the reset

state and is ready for service. The

tx_ready

latency for the TX

interface is 0. A 0 latency means that the TX FIFO can accept data on

the same clock cycle that

tx_ready

is asserted. This output is

synchronous to the

phy_mgmt_clk

clock domain. The Interlaken MAC

must wait for

tx_ready

before initiating data transfer (pre-fill pattern

or valid user data) on any lanes. The TX FIFO only captures input data

from the Interlaken MAC when

tx_ready

and

tx_parallel_data[65]

are both asserted.

For Quartus versions earlier than 12.0, the user is a required to pre-fill

the transmit FIFO. Do not use valid user data to pre-fill the transmit

FIFO.

The beginning of the pre-fill stage is marked by the assertion of

tx_ready

, before

tx_sync_done

is asserted. The pre-fill stage

should terminate when

tx_ready

is high and

tx_sync_done

changes

from Logic 0 to Logic 1 state. At this point, TX synchronization is

complete and valid TX data insertion can begin. TX synchronization is

not required for single-lane variants. Use the following Verilog HDL

assignment is for Quartus versions earlier than 12.0.

assign tx_parallel_data[65] =

(!tx_sync_done)?1'b1:tx_datain_bp[0];

tx_datain_bp<n>

Output

When asserted, indicates that Interlaken TX lane <n> interface is ready

to receive data for transmission. In multi-lane configurations, the

tx_datain_bp<n>

signals must be logically Ored. The latency on this

Avalon-ST interface is 0 cycles. The Interlaken MAC must only drive

valid user data on

tx_parallel_data<n>[64]

and

tx_parallel_data<n>[63:0]

data bus as soon as

tx_ready<n>

and

tx_sync_done

are both asserted. The

tx_datain_bp<n>

signal

is connected to the partial empty threshold of the TX FIFO, so that

when

tx_datain_bp<n>

is deasserted the TX FIFO back pressures

the Interlaken MAC. Stop sending TX data to the PHY when this signal

is deasserted.

The Interlaken MAC can continue driving data to the TX FIFO when

tx_datain_bp<n>

is asserted. The Interlaken MAC should gate

tx_parallel_data<n>[65],

which operates as a data_valid signal,

based on

tx_datain_bp<n>

. This output is synchronous to the

tx_coreclkin

clock domain. Or, you can also tie

tx_datain_bp<n>

directly to

tx_parallel_data<n>[65]

. For Quartus II releases prior

to 12.0, you must pre-fill the TX FIFO before

tx_sync_done

can be

asserted. Do not use valid data to pre-fill the TX FIFO. Use the

following Verilog HDL assignment for Quartus II releases prior to 12.0:

assign tx_parallel_data[65] =

(!tx_sync_done)?1'b1:tx_datain_bp[0];

tx_clkout

Output

Output clock from the TX PCS. The frequency of this clock equals the

Lane rate divided by 40, which is the PMA serialization factor.

Table 7–4. Avalon-ST TX Signals (Part 2 of 3)

Signal Name Direction Description

1 2 ... 138 139 140 141 142 143 144 145 146 147 148 ... 483 484

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