Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 15)

Chapter 1: Introduction 1–3

November 2012 Altera Corporation Altera Transceiver PHY IP Core

User Guide

For detailed information about these IP cores, refer to the following chapters:

■ Stratix V Transceiver Native PHY IP Core

■ Arria V Transceiver Native PHY IP Core

■ Arria V GZ Transceiver Native PHY IP Core

■ Cyclone V Transceiver Native PHY IP Core

■ Additional PHYs—These PHYs provide more flexible settings than the

protocol-specific transceiver PHYs. They include an Avalon

Memory-Mapped

(Avalon-MM) interface to access control and status registers and an Avalon

Streaming (Avalon-ST) interface to connect to the MAC for data transfer.

■ Custom PHY IP Core

■ Low Latency PHY IP Core

■ Deterministic Latency PHY IP Core

The following sections provide a brief introduction to the modules included in the

transceiver PHYs and the separately instantiated Transceiver Reconfiguration

Controller and Transceiver PHY Reset Controller IP Cores.

PCS

The PCS implements part of the physical layer specification for networking protocols.

Depending upon the protocol that you choose, the PCS may include many different

functions. Some of the most commonly included functions are: 8B/10B, 64B/66B, or

64B/67B encoding and decoding, rate matching and clock compensation, scrambling

and descrambling, word alignment, phase compensation, error monitoring, and

gearbox.

PMA

The PMA receives and transmits differential serial data on the device external pins.

The transmit (TX) channel supports programmable pre-emphasis and programmable

output differential voltage (V

). It converts parallel input data streams to serial data.

The receive (RX) channel supports offset cancellation to correct for process variation

and programmable equalization. It converts serial data to parallel data for processing

in the PCS. The PMA also includes a clock data recovery (CDR) module with separate

CDR logic for each RX channel.

Avalon-MM PHY Management

You can use the Avalon-MM PHY Management module to read and write the control

and status registers in the PCS and PMA for the protocol-specific transceiver PHY.

The Avalon-MM PHY Management module includes both Avalon-MM master and

slave ports and acts as a bridge. It transfers commands received from an embedded

controller on its slave port to its master port. The Avalon-MM PHY management

master interface connects the Avalon-MM slave ports of PCS and PMA registers and

the Transceiver Reconfiguration module, allowing you to manage these Avalon-MM

slave components through a simple, standard interface. (Refer to Transceiver PHY

Top-Level Modules.)

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