Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 245)

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–7

PMA Parameters

November 2012 Altera Corporation Altera Transceiver PHY IP Core

User Guide

TX PLL<n>

Table 12–5 allows you to define multiple TX PLLs for your Native PHY. The Native

PHY GUI provides a separate tab for each TXPLL.

Table 12–5. TX PLL Parameters

Parameter Range Description

PLL type CMU, ATX

You can select either the CMU or ATX PLL. the CMU PLL has a

larger frequency range than the ATX PLL. The ATX PLL is

designed to improve jitter performance and achieves lower

channel-to-channel skew; however, it supports a narrower range

of data rates and reference clock frequencies. Another advantage

of the ATX PLL is that it does not use a transceiver channel, while

the CMU PLL does.

Because the CMU PLL is more versatile, it is specified as the

default setting. An error message displays in the message pane if

the settings chosen for Data rate and Input clock frequency are

not supported for selected PLL.

PLL base data rate Device Dependent

Shows the base data rate of the clock input to the TX PLL.The

PLL base data rate is computed from the TX local clock division

factor multiplied by the Data rate.

Select a PLL base data rate that minimizes the number of PLLs

required to generate all the clocks for data transmission. By

selecting an appropriate PLL base data rate, you can change

data rates by changing the TX local clock division factor used by

the

clock generation block.

Reference clock frequency Device Dependent

Specifies the frequency of the reference clock for the Selected

reference clock source index you specify. You can define a single

frequency for each PLL. You can use the Transceiver

Reconfiguration Controller shown in Stratix V Native Transceiver

PHY IP Core to dynamically change the reference clock input to

the PLL.

Note that the list of frequencies updates dynamically when you

change the Data rate.

The Input clock frequency drop down menu is populated with all

valid frequencies derived as a function of the data rate and base

data rate. However, if fb_compensation is selected as the

bonding mode then the input reference clock frequency is limited

to the data rate divided by the PCS-PMA interface width.

Selected reference clock source 0–4

You can define up to 5 frequencies for the PLLs in your core. The

Reference clock frequency selected for index 0, is assigned to

TX PLL<0>. The Reference clock frequency selected for index 1,

is assigned to TX PLL<1>, and so on.

1 2 ... 240 241 242 243 244 245 246 247 248 249 250 ... 483 484

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