Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 134)

6–22 Chapter 6: XAUI PHY IP Core

Dynamic Reconfiguration for Arria V, Cyclone V and Stratix V Devices

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Table 6–16 describes the signals in the reconfiguration interface. If your XAUI PHY IP

Core includes a single transceiver quad, these signals are internal to the core. If your

design uses more than one quad, the reconfiguration signals are external.

Dynamic Reconfiguration for Arria V, Cyclone V and Stratix V Devices

The Arria V, Cyclone V, and Stratix V devices use the Transceiver Reconfiguration

Controller IP Core for dynamic reconfiguration. For more information about this IP

core, refer to Chapter 16, Transceiver Reconfiguration Controller IP Core.

Each channel and each TX PLL have separate dynamic reconfiguration interfaces. The

MegaWizard Plug-In Manager provides informational messages on the connectivity

of these interfaces. Example 6–2 shows the messages for a single transceiver quad.

Although you must initially create a separate reconfiguration interface for each

channel and TX PLL in your design, when the Quartus II software compiles your

design, it reduces the number of reconfiguration interfaces by merging

reconfiguration interfaces. The synthesized design typically includes a

reconfiguration interface for at least three channels because three channels share an

Avalon-MM slave interface which connects to the Transceiver Reconfiguration

Controller IP Core. Conversely, you cannot connect the three channels that share an

Avalon-MM interface to different Transceiver Reconfiguration Controller IP Cores.

Doing so causes a Fitter error. For more information, refer to“Transceiver

Reconfiguration Controller to PHY IP Connectivity”.

Logical Lane Assignment Restriction

If you are using ×6 or ×N bonding, transceiver dynamic reconfiguration requires that

you assign the starting channel number. Logical channel 0 should be assigned to

either physical transceiver channel 1 or channel 4 of a transceiver bank. However, if

you have already created a PCB with a different lane assignment for logical lane 0,

you can use the workaound shown in Example 6–3 to remove this restriction.

Example 6–3 redefines the

pma_bonding_master

parameter using the Quartus II

Table 6–16. Dynamic Reconfiguration Interface Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX devices

Signal Name Direction Description

reconfig_to_xcvr[3:0]

Input

Reconfiguration signals from the Transceiver Reconfiguration IP

Core to the XAUI transceiver.

reconfig_from_xcvr[<n>:0]

Output

Reconfiguration signals from the XAUI transceiver to the

Transceiver Reconfiguration IP Core. The size of this bus is

depends on the device. For the soft PCS in Stratix IV GX and GT

devices,

<n>

= 68 bits. For hard XAUI variants,

<n>

= 16. For

Stratix V devices, the number of bits depends on the number of

channels specified. Refer to Chapter 16, Transceiver

Reconfiguration Controller IP Core for more information.

Example 6–2. Informational Messages for the Transceiver Reconfiguration Interface

PHY IP will require 8 reconfiguration interfaces for connection to the external

reconfiguration controller.

Reconfiguration interface offsets 0-3 are connected to the transceiver channels.

Reconfiguration interface offsets 4-7 are connected to the transmit PLLs.

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