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8–20 Chapter 8: PHY IP Core for PCI Express (PIPE)

Enabling Dynamic PMA Tuning for PCIe Gen3

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Enabling Dynamic PMA Tuning for PCIe Gen3

“Section 4.2.3 Link Equalization Procedure for 8.0 GT/s Data Rate” in the PCI Express Base

Specification, Rev. 3.0 provides detailed information about the four-stage link

equalization procedure. However, in some instances you may want to override the

specified four-stage link equalization procedure to dynamically tune PMA settings.

Follow these steps to override Gen3 equalization:

1. Connect the Transceiver Reconfiguration Controller IP Core to your PHY IP Core

for PCI Express as shown in PCI Express PIPE IP Core Top-Level Modules.

2. For each transmitter port, use the Quartus II Assignment Editor to assign the

Transmitter VOD/Preemphasis Control Source the value RAM_CTL.

3. Recompile your design.

You can now use the Transceiver Reconfiguration Controller to change V

and

pre-emphasis settings.

Dynamic Reconfiguration

The calibration performed by the dynamic reconfiguration interface compensates for

variations due to process, voltage, and temperature (PVT). For Stratix V devices, each

channel and each TX PLL have separate dynamic reconfiguration interfaces. The

MegaWizard Plug-In Manager provides informational messages on the connectivity

of these interfaces. Example 8–1 shows the messages for a 8-channel PHY IP Core for

PCI Express (PIPE).

Although you must initially create a separate reconfiguration interface for each

channel and TX PLL in your design, when the Quartus II software compiles your

design, it reduces the total number of reconfiguration interfaces by merging

reconfiguration interfaces. The synthesized design typically includes a

reconfiguration interface for at least three channels because the three channels within

each transceiver triplet share a single physical Avalon-MM slave interface which

connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you

cannot connect the three channels that share this single physical Avalon-MM interface

to different Transceiver Reconfiguration Controllers. Doing so causes a Fitter error.

For more information, refer to“Transceiver Reconfiguration Controller to PHY IP

Connectivity”.

Example 8–1. Informational Messages for the Transceiver Reconfiguration Interface

PHY IP will require 9 reconfiguration interfaces for connection to the external

reconfiguration controller.

Reconfiguration interface offsets 0-7 are connected to the transceiver channels.

Reconfiguration interface offset 8 is connected to the transmit PLL.

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