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3–6 Chapter 3: 10GBASE-R PHY IP Core

Performance and Resource Utilization for Stratix IV Devices

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Performance and Resource Utilization for Stratix IV Devices

.Table 3–5 shows the typical expected device resource utilization for duplex channels

using the current version of the Quartus II software targeting a Stratix IV GT device.

The numbers of combinational ALUTs, logic registers, and memory bits are rounded

to the nearest 100.

Performance and Resource Utilization for Arria V GT Devices

Table 3–6 shows the resource utilization when targeting an Arria V

(5AGTFD7K3F4015) device. Resource utilization numbers reflect changes to the

resource utilization reporting starting in the Quartus II software v12.1 release for

28 nm device families and upcoming device families. The numbers of ALMs and logic

registers in Table 3–6 are rounded up to the nearest 100.

h For information about Quartus II resource utilization reporting, refer to Fitter

Resources Reports in the Quartus II Help.

Performance and Resource Utilization Arria V GZ and Stratix V Devices

Because the 10GBASE-R PHY is implemented in hard logic in Arria V GZ and

Stratix V devices, it uses less than 1% of the available ALMs, memory, primary and

secondary logic registers.

Table 3–7 lists the total latency for an Ethernet packet with a 9600 byte payload and an

inter-packet gap of 12 characters. The latency includes the number of cycles to

transmit the payload from the TX XGMII interface, through the TX PCS and PMA,

looping back through the RX PMA and PCS to the RX XGMII interface. (Stratix V

Clock Generation and Distribution illustrates this datapath.)

1 If latency is critical, Altera recommends designing your own soft 10GBASE-R PCS

and connecting to the Low Latency PHY IP Core.

Table 3–5. 10GBASE-R PHY Performance and Resource Utilization—Stratix IV GT Device

Channels Combinational ALUTs Logic Registers (Bits) Memory Bits

1 5200 4100 4700

4 15600 1300 18800

10 38100 32100 47500

Table 3–6. 10GBASE-R PHY Performance and Resource Utilization—Arria Device

Channels ALMs Primary Logic Registers Secondary Logic Registers Memory 10K

1 2800 3000 300 7

Table 3–7. Latency

PPM Difference Cycles

0 PPM 35

-200 PPM 35

+200 PPM 42

1 2 ... 23 24 25 26 27 28 29 30 31 32 33 ... 483 484

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Altera UG-01080 Betriebsanweisung Seite 28