Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 148)

7–12 Chapter 7: Interlaken PHY IP Core

Optional Clocks for Deskew

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Optional Clocks for Deskew

Table 7–8 describes the optional clocks that you can create to reduce clock skew.

The Avalon-MM PHY management interface provides access to the Interlaken PCS

and PMA registers, resets, error handling, and serial loopback controls. You can use

an embedded controller acting as an Avalon-MM master to send read and write

commands to this Avalon-MM slave interface. Table 7–9 describes the signals that

comprise the Avalon-MM management interface.

Table 7–8. Serial Interface

Signal Name Direction Description

tx_coreclkin

Input

When enabled

tx_coreclkin

is available as input port which drives

the write side of TX FIFO. Altera recommends using this clock to

reduce clock skew. The minimum frequency is data rate/67. Using a

lower frequency will underflow the TX FIFO causing the Frame

Generators to go into a unrecoverable out of alignment state and

insert Skip Words into the lane. If the Interlaken TX FIFO underflows,

the alignment state machine tries to recover continuously. When

disabled,

tx_clkout

drives the write side the TX FIFO.

tx_coreclkin

must be used when the number of lanes is greater

than 1.

rx_coreclkin

Input

When enabled,

rx_coreclkin

is available as input port which drives

the read side of RX FIFO. Altera recommends using this clock to

reduce clock skew. You should use a minimum frequency of lane data

rate/ 67 to drive

rx_coreclkin

. Using a lower frequency overflows

the RX FIFO corrupting the received data.When disabled,

rx_user_clkout,

which is the master

rx_clkout

for all the

bonded receiver lanes, is internally routed to drive the read side the

RX FIFO.

Table 7–9. Avalon-MM PCS Management Interface (Part 1 of 2)

Signal Name Direction Description

phy_mgmt_clk

Input

Avalon-MM clock input.

There is no frequency restriction for Stratix V devices; however, if you

plan to use the same clock for the PHY management interface and

transceiver reconfiguration, you must restrict the frequency range of

phy_mgmt_clk

to 100–150 MHz to meet the specification for the

transceiver reconfiguration clock.

phy_mgmt_clk_reset

Input

Global reset signal that resets the entire Interlaken PHY. This signal is

active high and level sensitive.

When the Interlaken PHY IP connects to the Transceiver PHY

Reconfiguration Controller IP Core, the Transceiver PHY

Reconfiguration Controller

mgmt_rst_reset

signal must be

simultaneously asserted with the

phy_mgmt_clk_reset

signal to

bring the Frame Generators in the link into alignment. This is a

mandatory requirement. Failure to comply to this requirement will

result in excessive transmit lane-to-lane skew in the Interlaken link.

phy_mgmt_addr[8:0]

Input 9-bit Avalon-MM address.

1 2 ... 143 144 145 146 147 148 149 150 151 152 153 ... 483 484

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