Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 94
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4–6 Chapter 4: SDI Audio IP Cores
SDI Audio Embed MegaCore Function
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Table 4–5 lists the Avalon-ST audio signals when you instantiate the SDI Audio
Embed MegaCore function in SOPC Builder.
Table 4–6 lists the direct control interface signals. These signals are exposed as ports if
you turn off the Include Avalon-MM Control Interface parameter.
Table 4–5. Avalon-ST Audio Signals for SDI Audio Embed MegaCore Function
Signal Width Direction Description
aud(n)_clk
[0:0] Input
Clocked audio clock. All the audio input signals are
synchronous to this clock.
aud(n)_ready
[0:0] Output
Avalon-ST ready signal. Assert this signal when the
device is able to receive data.
aud(n)_valid
[0:0] Input
Avalon-ST valid signal. The MegaCore function
asserts this signal when it receives data.
aud(n)_sop
[0:0] Input
Avalon-ST start of packet signal. The MegaCore
function asserts this signal when it is starting a new
frame.
aud(n)_eop
[0:0] Input
Avalon-ST end of packet signal. The MegaCore
function asserts this signal when it is ending a frame.
aud(n)_channel
[7:0] Input
Avalon-ST select signal. Use this signal to select a
specific channel.
aud(n)_data
[23:0] Input Avalon-ST data bus. This bus transfers data.
Note to Table 4–5:
(1) (n) represents the channel number.
Table 4–6. Direct Control Interface Signals (Part 1 of 2)
Signal Width Direction Description
reg_clk
[0:0] Input Clock for the direct control interface.
audio_control
[7:0] Input
This signal does the same function as the audio control
register in Table 4–9.
extended_control
[7:0] Input
This signal does the same function as the extended control
register in Table 4–9.
video_status
[7:0] Output
This signal does the same function as the video status
register in Table 4–9.
audio_status
[7:0] Output
This signal does the same function as the audio status
register in Table 4–9.
cs_control
[15:0] Input
This signal does the same function as the channel status
control registers in Table 4–9.
sine_freq_ch1
[7:0] Input
This signal does the same function as the sine channel 1
frequency register in Table 4–9.
sine_freq_ch2
[7:0] Input
This signal does the same function as the sine channel 2
frequency register in Table 4–9.
sine_freq_ch3
[7:0] Input
This signal does the same function as the sine channel 3
frequency register in Table 4–9.
sine_freq_ch4
[7:0] Input
This signal does the same function as the sine channel 4
frequency register in Table 4–9.
csram_addr
[5:0] Input Channel status RAM address.
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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