Altera 50G Interlaken MegaCore Function Bedienungsanleitung

50G Interlaken MegaCore Function UserGuideLast updated for Altera Complete Design Suite: 15.0SubscribeSend FeedbackUG-011402015.05.04101 Innovation Dr

Getting Started With the 50G Interlaken IP Core22015.05.04UG-01140SubscribeSend FeedbackThe following sections explain how to install, parameterize, s

• Simulate the behavior of a licensed IP core in your system.• Verify the functionality, size, and speed of the IP core quickly and easily.• Generate

a. Click Finish. The Generation dialog box appears.b. Click Exit. The parameter editor adds the top-level .qsys file to the current project automatica

If you select the Verilog HDL for synthesis and simulation models, the demonstration testbench andexample design files are located in <your_ip>_

Figure 2-3: IP Core Generated Files<your_ip >.cmp - VHDL component declaration file<your_ip >.ppf - XML I/O pin information file<your

Simulating the50G Interlaken IP CoreYou can simulate your 50G Interlaken MegaCore function variation using any of the vendor-specific IEEEencrypted fu

Transceiver Logical Channel NumberingIn Arria V and Stratix V devices, logical channel numbering starts from zero. The logical channelnumbering starts

Transceiver Block Number Logical Channel Number inDeviceDirection Interlaken Lane Number inIP Core20 TX PLL 2219TXRX18TXRX17TXRX16TXRX15TXRX14TXRX13 T

Transceiver Block Number Logical Channel Number inDeviceDirection Interlaken Lane Number inIP Core112TX7RX11TX(Left available forCMU PLL)RX10TX6RX9TX5

Transceiver Block Number Logical Channel Number inDeviceDirection Interlaken Lane Number inIP Core05TX3RX4TX(Left available forCMU PLL)RX3TX2RX2TX1RX1

ContentsAbout This MegaCore Function... 1-1Features...

The following simple instructions show you how to instantiate an Altera Transceiver ReconfigurationController and how to connect the design blocks:Gen

Figure 2-4: Typical Connection of Reconfiguration Controller to 50G Interlaken IP Core50G InterlakenMegaCoreFunctionReconfigurationControllermgmt_clk_

You must connect the external PLL signals and the Arria 10 50G Interlaken IP core transceiver Tx PLLinterface signals according to the following rules

• Pin Assignments on page 2-6• Arria 10 External PLL Interface Signals on page 5-15• Arria 10 Transceiver PHY User GuideInformation about the correspo

50G Interlaken IP Core Parameter Settings32015.05.04UG-01140SubscribeSend FeedbackYou customize the 50G Interlaken IP core by specifying parameters in

Related Information• 50G Interlaken IP Core Clock Signals on page 4-5• 50G Interlaken IP Core Clock Interface Signals on page 5-1Number of Calendar Pa

and enables the 50G Interlaken IP core to perform enhanced scheduling based on the BurstMax andBurstMin settings. If the data bursts that arrive on th

Functional Description42015.05.04UG-01140SubscribeSend FeedbackThe 50G Interlaken MegaCore function provides the functionality described in the Interl

The 50G Interlaken MegaCore function value for the Interlaken BurstMax parameter is determined by thevalue you specify on the burst_max_in input signa

Arria 10 Transceiver Reconfiguration Interface on page 4-3Transceiver Reconfiguration Controller Interface50G Interlaken IP core variations that targe

50G Interlaken IP Core Clock Signals...4-5IP Core Reset...

High Level Block DiagramFigure 4-1: 50G Interlaken Block Diagramirx_chan[7:0]irx_num_valid[2:0]irx_sobirx_eobirx_sopirx_eopbits[3:0]irx_dout_words[255

50G Interlaken IP Core Clock SignalsTable 4-1: 50G Interlaken IP Core ClocksClock Name Descriptionpll_ref_clkReference clock for the RX transceiver PL

Figure 4-2: 50G Interlaken IP Core Transceiver Initialization SequenceThe internal initialization sequence implemented by the reset controller include

• Arria 10 Transceiver PHY User GuideFor more information about the Altera reset controller that is included in Arria 10 variations of the50G Interlak

In Packet mode, the 50G Interlaken IP Core performs Optional Scheduling Enhancement based onSection 5.3.2.1.1 of the Interlaken Protocol Specification

Figure 4-4: Packet Transfer on Transmit Interface in Interleaved ModeThis example illustrates the expected behavior of the 50G Interlaken IP core appl

4'b1011 on itx_eopbits, to tell the IP core that in this clock cycle, the two most significant words of thedata symbol contain valid data and the

During the SOP cycle (labeled with data value d1) and the cycle that follows the SOP cycle (labeled withdata value d2), you must hold the value of itx

supports your design in achieving timing closure more easily. In any case you must ensure that you holditx_num_valid at the value of 0 when you are no

Control Word Reset Calendar Bit (bit [56]) In-Band Flow Control Bits (bits [55:40])Second 0 16'b0010001000100010 (16'h2222)Third 0 16'b

Counter Reset Bits...9-2Inclu

50G Interlaken IP Core TX PCS on page 4-1450G Interlaken IP Core TX PMA on page 4-1450G Interlaken IP Core TX Transmit BufferThe 50G Interlaken MegaCo

50G Interlaken IP Core Receiver Side ExampleThe 50G Interlaken IP Core can generate interleaved data transfers on the RX user data transfer interface.

also not end of packet data. This data follows the data burst transfered in cycles 1 and 2, within the samepacket the IP core is sending to channel 2.

potentially errored packet, and the application can rely on the fact that if irx_err is not asserted andirx_eopbits has a value other than 4'b000

following clock cycle, labeled with data value d3, the 50G Interlaken IP Core holds the following values oncritical output signals:• itx_num_valid[2:0

50G Interlaken IP Core Receive Path BlocksFigure 4-10: 50G Interlaken IP Core Receive Pathirx_chan[7:0]irx_num_valid[2:0]irx_sobirx_eobirx_sopirx_eopb

The 50G Interlaken MegaCore function RX MAC performs the following functions:• Data de-striping, including lane alignment and burst assembly from the

50G Interlaken MegaCore Function Signals52015.05.04UG-01140SubscribeSend FeedbackThe 50G Interlaken MegaCore function communicates with the surroundin

Signal Name Direction Width(Bits)Descriptionclk_rx_common Output 1 Master recovered lane clock. The Interlaken specifica‐tion requires all incoming la

Signal Name Direction Width(Bits)Descriptionreset_n Input 1 Active-low reset signal for the 50G Interlaken IP core.Altera recommends that you hold thi

About This MegaCore Function12015.05.04UG-01140SubscribeSend FeedbackInterlaken is a high-speed serial communication protocol for chip-to-chip packet

50G Interlaken IP Core User Data Transfer Interface SignalsTable 5-3: 50G Interlaken IP Core User Data Transfer InterfaceSignal Name Direction Width(B

Signal Name Direction Width(Bits)Descriptionitx_eopbitsInput 4 Indicates whether the current data symbol contains the end of a packet(EOP) with or wit

Signal Name Direction Width(Bits)Descriptionitx_calendarInput 16 N Multiple pages (16 bits per page) of calendar input bits. The50G Interlaken IP Core

Signal Name Direction Width(Bits)Descriptionirx_sop Output 1 Indicates the current data symbol on irx_dout_words contains thestart of a packet (SOP).

Signal Name Direction Width(Bits)Descriptionirx_err Output 1Indicates an errored packet. This signal is valid only when bothirx_num_valid[2:0] and irx

Signal Name Direction Width (Bits) Descriptionburst_short_in Input 4 Encodes the BurstShort parameter for the IPcore.The 50G Interlaken IP core suppor

Signal Name Direction Width (Bits) Descriptionitx_hungry Output 1 A dynamic status flag indicating that adownstream buffer which supplies data to theP

Signal Name Direction Width (Bits) Descriptioncrc24_err Output 1 A CRC24 error flag covering both control wordand data word. This signal does not asso

Related InformationRXFIFO Address Width on page 9-2Information about programming the depth of the Reassembly FIFO with the RXFIFO_ADDR_WIDTHparameter.

If you do not use the management interface, drive the management inputs as follows:• mm_clk must connect to a stable clock. However, the clock signal

• Supports up to 256 logical channels in out-of-the-box configuration.• Supports optional user-controlled in-band flow control with 1, 2, 4, 8, or 16

Device Dependent SignalsSome of the 50G Interlaken MegaCore function signals depend on the device that your variation targets.Variations that target a

Arria 10 External PLL Interface Signals50G Interlaken IP core variations that target an Arria 10 device require an external transceiver PLL tofunction

Signal Name Direction Width(Bits)Descriptionreconfig_write Input 1 Write access to the Arria 10 hard PCS registers.reconfig_address Input 13 Address t

50G Interlaken IP Core Register Map62015.05.04UG-01140SubscribeSend FeedbackThe 50G Interlaken IP core control registers are 32 bits wide and are acce

Offset Name R/W Description9'h4 TX_EMPTY RO [NUM_LANES–1:0] – Transmit FIFO status (empty)9'h5 TX_FULL RO [NUM_LANES–1:0] – Transmit FIFO st

Offset Name R/W Description9'h12LOOPBACKRW [NUM_LANES–1:0] – For each lane, write a 1 to activateinternal TX to RX serial loopback mode, or write

Offset Name R/W Description9'h25CRC2RO 4 bit counters indicating CRC errors in lanes23,22,21,20,19,18,17,16.These will saturate at F, and you cle

Offset Name R/W Description9'h38CRC32_ERR_INJECTRW [NUM_LANES–1:0] - When a bit has the value of 1, the IPcore injects CRC32 errors on the corres

50G Interlaken IP Core Testbench72015.05.04UG-01140SubscribeSend FeedbackWhen you generate an 50G Interlaken IP core variation with Verilog HDLsynthes

In Arria 10 variations, the example design includes external TX PLLs. You can examine the clear text filesto view sample code that implements one poss

Device Family SupportOther device families No supportIP Core VerificationBefore releasing a version of the 50G Interlaken IP core, Altera runs compreh

Testbench Simulation BehaviorDuring simulation, the 50G Interlaken IP core testbench performs the following actions:1. Resets the 50G Interlaken IP co

a. <variation>_sim/ilk_core_50g/testbench for Arria V GZ and Stratix V IP core variations.b. <variation>/ilk_core_50g_<version>/sim/

50G Interlaken IP Core Test Features82015.05.04UG-01140SubscribeSend FeedbackYour 50G Interlaken IP core supports the following test features:Internal

PRBS Generation and ValidationThe 50G Interlaken IP core supports generation and validation of several predetermined pseudo-randombinary sequences (PR

Table 8-2: Programming the Hard PCS Registers in Arria V and Stratix V DevicesTo turn on the PRBS feature in the hard PCS, you must program the follow

receive PRBS input, you can check the receive PRBS status in the 50G Interlaken IP core PRBS statusregisters (RX_PRBS_DONE, RX_PRBS_ERR, and RX_PRBS_C

TX Register Offset Bits Meaning Action2 0x7[2] Invert TX channels Set this bit to the value of 0 to specify thatthe outgoing PRBS be inverted, or set

RX Register Offset Bits Meaning Action2 0xB[1]Enable 10G PCS mode Set this bit to the value of 1 to specify thePCS is in 10G mode.[3:2] Verifier count

Related Information• 50G Interlaken IP Core Register Map on page 6-1Describes the PRBS status registers and the soft reset register.• Arria 10 Transce

Advanced Parameter Settings92015.05.04UG-01140SubscribeSend FeedbackAdvanced users can further customize the 50G Interlaken IP core by modifying hidde

Related Information• Fitter Resources Reports in the Quartus II HelpInformation about Quartus II resource utilization reporting for 28-nm devices, inc

Counter Reset BitsThe Counter Reset Bits parameter (CNTR_BITS) specifies the counter configuration for the IP coreinternal reset sequence.This paramet

Figure 9-1: Straight Lane OrderLane N...Lane 2Lane 1Lane 0• Swapped Lane order. The transmitter sends Interlaken blocks sequentially across the lanes

Use ATX or CMU PLLThe USE_ATX parameter specifies whether the transceivers use the ATX PLL or the CMU PLL. If thisparameter has the value of 0, the 50

Table 9-1: Files to Edit to Modify the Value of a Hidden ParameterIn each entry, the first file controls the RTL parameter value for synthesis, and th

Out-of-Band Flow Control in the 50G InterlakenMegaCore Function102015.05.04UG-01140SubscribeSend FeedbackThe 50G Interlaken MegaCore function includes

Related InformationInterlaken Protocol Specification, Revision 1.2Out-of-Band Flow Control Block ClocksTable 10-1: 50G Interlaken MegaCore Function Ou

Specification, Revision 1.2. The TX Out-of-Band Flow Control Block Signals for Application Use tabledescribes the signals on the application side of t

RX Out-of-Band Flow Control SignalsThe receive out-of-band flow control interface receives input flow-control clock, data, and sync signalsand sends o

Signal Name Direction Width(Bits)Descriptioncalendar Output 16 Calendar bits received from an upstream out-of-bandTX block on fc_data.calendar_update

Performance and Fmax Requirements for 40GEthernet TrafficA2015.05.04UG-01140SubscribeSend FeedbackTo achieve 40G Ethernet line rates through the appli

Altera verifies that the current version of the Quartus II software compiles the previous version of eachMegaCore function, if this MegaCore function

Figure A-2: Packet Processing Requirements32Bytes32Bytes64 Bytes at 200 MHz2561 232Bytes32Bytes65 - 96 Bytes in 15 ns2561 - 32BytesA 65-byte packet co

Additional InformationB2015.05.04UG-01140SubscribeSend FeedbackThis section provides additional information about the document and Altera.Document Rev

Date ACDS Version Changes Made• Added information about turning on and off loopback mode in two newsections, External Loopback Mode and Internal Seria

How to Contact AlteraTable B-2: How to Contact AlteraTo locate the most up-to-date information about Altera products, refer to this table. You can als

Visual Cue MeaningItalic Type with Initial Capital Letters Indicate document titles. For example, Stratix VDesign Guidelines.italic type Indicates va