Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 61
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Chapter 3: Functional Description 3–31
Block Description
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Figure 3–19 shows the block diagram of how the SDI MegaCore function and the
ALT2GXB_RECONFIG megafunction are connected.
The ALT2GXB_RECONFIG block handles the programming of the ROM contents into
the transceiver megafunction. It performs data serialization and also handles
protection of certain data bits in the serial stream. You can only connect this block to
the reprogramming ports of the transceiver instance.
The ROM holds the transceiver setting information for the 3G-SDI video standard. As
the setup for SD-SDI is similar to 3G-SDI, only two settings are required: one for
SD-SDI and 3G-SDI, and one for HD-SDI.
The reconfiguration control and intercept user logic selects the correct transceiver
setting and also provides the handshaking between the SDI MegaCore function and
the ALT2GXB_RECONFIG block. The logic modifies the ROM read data when it reads
word 23 for all devices, barring Arria II GX and Stratix IV devices. For Arria II GX and
Stratix IV devices, the logic modifies the ROM read data when it reads word 29. For
examples, refer to the intercept logic,
example\s2gx_tr\source\sdi_dprio\sdi_mif_intercept.v and
example\a2gx_tr\source\sdi_dprio_siv\sdi_mif_intercept_siv.v.
Figure 3–19. Transceiver Dynamic Reconfiguration for Receiver Block Diagram
Note to Figure 3–19:
(1) The
SDI_START_RECONFIG
and
SDI_RECONFIG_DONE
signals are not connected to the SDI MegaCore transmitter.
ALT2GXB
RECONFIG_INST
RECONFIG Control
and Intercept
User Logic
ALT2GXB_INST
Protocol
SDI IP Core - Receiver
RECONFIG_TOGXB[2:0]
ROM_CLK_ENABLE
ROM_ADDRESS
ROM_DATA_OUT
if (ROM_ADDRESS = RX PMA)
select_hd
User Logic
Encrypted RECONFIG Megafunction
Encrypted SDI IP Core
HD: M, L value
3G/SD: M, L value
ROM (Hold MIF)
3G by default
1
0
0
1
RECONFIG_FROMGXB[0]
SDI_RECONFIG_DONE (1)
SDI_START_RECONFIG (1)
RX_STD
ALT2GXB_INST
Protocol
SDI IP Core - Duplex
ALT2GXB_INST
Protocol
SDI IP Core - Transmitter
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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