Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 38
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3–8 Chapter 3: Functional Description
Block Description
Serial Digital Interface (SDI) MegaCore Function February 2013 Altera Corporation
User Guide
Table 3–2 lists the bit allocation for
rxdata
.
The receiver interface extracts and tracks the F, V, and H timing signals in the received
data. Active picture and ancillary data words are also identified for your use.
For HD-SDI, the received CRC is checked for the luma and chroma channels. The LN
is also extracted and provided as an output from the design.
NRZI Decoding and Descrambling
The descrambler module provides the channel decoding function that is common to
both SDI and HD-SDI. It implements the NRZI decoding followed by the required
descrambling. The algorithm indicated by SMPTE259M figure C.1 is iteratively
applied to the receiver data, with the LSB processed first.
Word Alignment
The aligner word aligns the descrambled receiver data such that the bit order of the
output data is the same as that of the original video data.
The EAV and SAV sequences determine the correct word alignment. Table 3–3 lists the
pattern for each standard.
The aligner matches the selected pattern in the descrambled receiver data. If the
pattern is detected at any of the possible word alignments, then a flag is raised and the
matched alignment is indicated. This process is applied continuously to the receiver
data.
The second stage of the aligner determines the correct word alignment for the data. It
looks for three consecutive TRSs with the same alignment, and then stores that
alignment. If two consecutive TRSs are subsequently detected with a different
alignment, then this new alignment is stored.
The final stage of the aligner applies a barrel shift function to the received data to
generate the correctly aligned parallel word output. For this SDI MegaCore function,
the barrel shifter allows the design to instantly switch from one alignment to another.
Table 3–2. Bit Allocation for rxdata for Supported Video Standards
rxdata SD-SDI HD-SDI 3G-SDI Level A 3G-SDI Level B
[19:10] Unused Y Y
Cb, Y, Cr, Y
multiplex (link A)
[9:0]
Cb, Y, Cr, Y
multiplex
CC
Cb, Y, Cr, Y
multiplex (link B)
Table 3–3. EAV and SAV Sequences
Video Standard EAV and SAV Sequences
SDI
3FF 000 000
HD-SDI
3FF 3FF 000 000 000 000
3G-SDI Level A
3FF 3FF 000 000 000 000
3G-SDI Level B
3FF 3FF 3FF 3FF 000 000 000 000 000 000 000 000
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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