Altera Serial Digital Interface (SDI) MegaCore Function Bedienungsanleitung Seite 77
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Chapter 3: Functional Description 3–47
Signals
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Figure 3–29 through Figure 3–37 show the behavior of some signals in Table 3–16.
Figure 3–28. Interface Signals for SDI Triple Standard Duplex Instance
Figure 3–29. Power-up Reset for the Receiver
Figure 3–30. Power-up Reset for the Transmitter
Note to Figure 3–30:
(1) Internally synchronized reset for the transmit circuits.
SDI Triple Standard Duplex Instance
rx_clk
rxdata[19:0]
rx_data_valid_out[1:0]
rx_std_flag_hd_sdn[0:0]
rx_status[10:0]
rx_std[1:0]
rx_trs
rx_eav
rx_xyz
xyz_valid
rx_anc_data[19:0]
rx_anc_valid[3:0]
rx_anc_error[3:0]
rx_video_format[7:0]
sdi_tx[0:0]
tx_status[0:0]
gxb_tx_clkout[0:0]
sdi_reconfig_fromgxb[16:0]
sdi_start_reconfig
rst_rx
rst_tx
rx_serial_refclk
refclk_rate
tx_serial_refclk
tx_serial_reflclk1 (optional)
tx_pclk
sdi_rx[0:0]
en_sync_switch
enable_hd_search
enable_sd_search
enable_3g_search
txdata[19:0]
tx_std[1:0]
tx_trs[0:0]
tx_ln[21:0]
enable_ln[0:0]
enable_crc[0:0]
gxb2_cal_clk/gxb4_cal_clk
sdi_reconfig_clk
sdi_reconfig_togxb[3:0]
sdi_reconfig_done
sdi_gxb_powerdown
rst_rx
rx_serial_refclk (74.25MHz)
rst_tx
0100
tx_pclk(74.25MHz)
tx_std[1:0]
rst_tx_sync (1)
Figure 3–31. Behavior of tx_std, tx_trs, and tx_ln Signals—425MA
tx_trs
txdata[19:10]
txdata[9:0]
tx_std[1:0]
tx_ln[21:11]
tx_pclk
3FF(Y) 000(Y) 000(Y) XYZ(Y)
3FF(C
11
) 000(C) 000(C XYZ(C)
11’d0
tx_ln[10:0]
11’d1 11’d2
000(Y) 000(Y) XYZ(Y)
000(C) 000(C XYZ(C)
3FF(Y)
3FF(C)
000(Y) 000(Y) XYZ(Y)
000(C) 000(C XYZ(C)
3FF(Y)
3FF(C)
EAV SAV
EAV
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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